It is the second day of the week-long symposium, but the first day of its star attraction, the Optical Microlithography conference. That means one room was packed to overflowing, while the others felt a bit cavernous. Most of the papers were good, though a few were nothing but marketing fluff – it is inevitable I think. Tuesday was also the beginning of the two-day technical exhibit, aka company booths. It is amazing how much money a company will spend for booth presence at this conference without much possibility of a return on that investment. Sure, for a litho-focused company exhibiting here is much, much better than wasting your time at a SEMICON show; still it is mostly just a bunch of marketing types hanging around trying to keep their competitors from looking over the booth.

Candidate for Worst Paper Award
This conference is full of good papers. But it is also full of bad ones. There are the marketing papers, really just sales pitches for some product where their fear of giving too much information to the competitors outweighs their desire to inform their customers – or maybe they really don’t have any information to give. Then there are the authors that ran out of time, the experiments didn’t get finished, and so at most we get to see intermediate results (OK, I am guilty of having done that a time or two myself). Some presenters are just plain bad (but I admire anyone with the guts to get up there and try just the same). But today I saw the worst of the worst. I guy gave a paper on CD variations without showing a single CD value! How could this happen, you ask? He had 20 graphs showing squares, circles, and dots connected by wavering lines spread across the page, but not a single y-axis had a number on it. It is obvious what happened. His management made him erase all the numbers. Maybe they thought their stock price would go down if the world realized they were making chips that included CD variations. In any case, we saw an entire paper based solely on the analysis of data but without any data. It shouldn’t have been given. My advice to all would-be authors: If your bone-head manager will let you give a paper only if you don’t show any data, pull the paper. Our time is too valuable to listen to nothing.

Keynote or Key Node?
The conference began with three fairly good keynote talks. But Yan Borodovsky set me off, inevitably enough, by touch on one of my pet peeves. Intel has for several years now bragged about staying on a two year cycle of technology node advances while the rest of the industry says cycles are slowing to three years. They recently announced a working 45nm node SRAM and industry pundits hailed their technology lead. But what does that mean, exactly, a 45nm node device? Are there any 45nm dimensions involved? Historically (ten years ago or more), the node name was equal to half of the smallest pitch on the critical level (metal 1 usually contains the smallest pitch on the chip since it is the mask level that controls the die size). But that was then. Now, node names have marketing value. Press releases and market analysts extol the importance of getting to the next node. It was inevitable, I suppose – node names became too important to be left to the engineers to define. They’ve been taken over by the marketing departments. So how does Intel define the 45nm node? Very simple – it the technology used two years after they began what they defined as the 65nm node. There’s no magic in the node name, and no information either. So what about pitch, the smallest line/space repeating distance on the chip? It seems that Intel is reducing pitch by about 30% every three years. Go figure.

Tomorrow begins the biggest event of the year for those of us with the arcane title of lithographer. In particular, “semiconductor lithographer”, since we don’t deal in art prints but rather work with $20M cameras that print features a few tens of nanometers wide. (But don’t confuse us with those nanotechnology types – we make products not research proposals). It’s the start of the week-long Microlithography Symposium, six separate conferences (five of them in parallel on Thursday!) with well over 150 papers a day and several thousand attendees.
This is the 22nd time I’ve been to this conference (don’t say it, I already know how old I am), and it wasn’t always like this. When I first came here in 1985 there were three separate conferences (and no parallel sessions – that headache didn’t start until the next year), each with about 30 – 40 papers. The number of attendees was a few hundred, not thousands, and we comfortably listened to papers predicting the inevitability of submicron manufacturing in the tiny Santa Clara Marriott. The first SPIE lithography conference (before my time, thank you very much) was exactly 30 years ago and had a total of 26 papers. Lithography was so much simpler then.
Growth of this conference has paralleled growth in the semiconductor industry. As we outgrew the Marriott (I remember breaks where it took 15 minutes just to push through the crowd to get to a bathroom), the conference moved to downtown San Jose and the Fairmont hotel. This became a favorite location with many after-hours spots within walking distance. I’m sure the locals were quite dismayed when whole sessions of geeky lithographers continued their technical discussions at the Gordon Biersch Microbrewery each night (Imagine the scene: “X-ray will never work, I tell you!” “What do you know – you’ve spent your entire career sniffing photoresist solvent.” “Oh yea, well at least I’ve actually made a chip that works!”). But we eventually outgrew this comfortable home as well and moved to the Santa Clara Convention Center. While the bar at the Westin hotel was a favorite, it just wasn’t the same. You couldn’t walk anywhere and there just weren’t enough restaurants for the growing crowds of hungry lithographers. Last year we moved back to San Jose and its bigger downtown convention center.
And so we begin. In the morning we start with the keynote speakers, and a massive week-long effort to cram as much information into our tiny little heads as we can possibly hold, hoping they won’t explode by Friday.

I’m new to the blogging business, but as far as I know there are no blogs on semiconductor microlithography. Maybe there is a reason for that. Maybe no one needs or wants a blog on lithography. But maybe the time is right. We’ll see. In any case, this is the launch of my litho blog. Just in time for the biggest litho conference of the year, the SPIE Microlithography Symposium, February 19-24.
So here is my plan. At the end of each day of the conference, I’ll write a blog on what I think about what happened that day. Assuming that my brain is still functioning adequately to do so after a full day of technical papers. In any case, I hope to have something insightful to say, or at least something entertaining. If you’re interested, tune in.