I bounced all over the conference on Thursday (the last day), from Tim Brunner\u2019s paper predicting focus and overlay performance based on measured wafer bow and thickness, to Derk Brouns\u2019s update on an EUV pellicle.\u00a0 Nelson Felix of IBM discussed early use of EUV lithography for 10-nm and 7-nm node logic devices (as opposed to the high-k1 results reported by Intel on their 14-nm node).\u00a0 The data-packed paper deserves much further study and I hope his proceedings paper contains all the information from his presentation.\u00a0 He mentioned the rule of thumb, commonly discussed this week, that if EUV throughput can get above a reliable 60 wafers per hour, EUV is cost effective compared to combining three 193 immersion patterns.\u00a0 All such calculations assume many things, not all of which I was able to catch from the talk, that greatly affect the outcome.\u00a0 I\u2019m sure that equal yield is assumed (a standard assumption for cost calculations), but we also need to know the dose that was assumed.\u00a0 Nelson mentioned that while printing 36-nm-pitch lines and spaces, going to a dose of 35 mJ\/cm2 produced a noticeable yield improvement compared to a 30 mJ\/cm2 dose.\u00a0 I wish that we might see more data like this in the future, since we desperately need to understand the yield\/dose trade-off.<\/p>\n
Jo Finders of ASML gave an excellent talk, emphasizing what many resist companies don\u2019t quite get:\u00a0 the quality of the image coming from the scanner matters a lot.\u00a0 For decades, lithographers have focused on optimizing masks and illumination to maximize the NILS (normalized image log-slope) of the image.\u00a0 Exposure latitude is proportional to NILS, so every little bit of improvement matters.\u00a0 Early EUV work was at larger k1 values, and many people were not yet concerned with process windows, so NILS did not get as much attention.\u00a0 But Jo reminded us of something we should never forget:\u00a0 LER, LWR and the local critical dimension uniformity (LCDU) that is caused by that roughness are all inversely proportional to NILS.\u00a0 Thus, for a given resist material at a given exposure dose, the easiest way to lower LER and LCDU is to increase the NILS, using classical approaches like illumination optimization.\u00a0 Of course, everyone should be following Jo Finder\u2019s advice.\u00a0 We also have to be aware that any roughness measurements must be made at the same NILS to be comparable \u2013 something almost no one does.\u00a0 The RLS (Resolution-LER-Sensitivity) trade-off should always be NILS corrected.\u00a0 Another option is to use the LER\/LWR resist metric that I proposed, though it seems not to have caught on since I published<\/a> it in 2014.\u00a0 Still, that metric is also NILS dependent and so NILS must be controlled in order to make comparisons.\u00a0 One way to do so is to use a reference image, such as the interferometric images produced at Paul Scherrer Institut.<\/p>\n On another topic, ASML and Nikon described the performance of their latest 193 immersion scanners.\u00a0 Overlay, focus control, and throughput on these new tools are very impressive.\u00a0 Tool productivity has increased by a factor of 2 in the last 7 years or so, and I wonder where continued productivity improvements will come from.\u00a0 A very difficult problem.<\/p>\n The last paper I attended was on detailed characterization of roughness measurements.\u00a0 My friend and roughness expert Vassilios Constantoudis could not make it this year, so his co-author Hari Pathangi did a good job of delivering the paper for him.\u00a0 Building on the earlier work of Ricardo Ruiz, this paper explored the correlation of roughness from feature to feature for both SAxP and DSA. \u00a0(I hope you have been reading this blog all week, because as you can see I am now dropping acronyms as if I learned them in elementary school).\u00a0 For these techniques we must look not just at edge-to-edge correlations, but feature-to-feature correlations across multiple pitches.<\/p>\n So what are my impressions of the symposium overall?\u00a0 This was a year of important but incremental progress.\u00a0 Let\u2019s look at how various technologies are trending.<\/p>\n Trending Up:<\/strong><\/p>\n EUV lithography<\/strong> has made important progress over the last year and the mood among many is more positive (especially since two years ago).\u00a0 Now that the 80W sources in the field are running in a moderately reliable fashion, learning in the fabs has begun in earnest.\u00a0 ASML has demonstrated a 200W source, but the delta between lab demonstration and reliable performance in the field is a great one.\u00a0 The key question for the source will be when do customers get their next upgrade?\u00a0 Will it be 100W by the end of the year?<\/p>\n Nanoimprint lithography<\/strong> (NIL) has made lonely progress at Canon (since they bought Molecular Imprints) and Toshiba, with SK Hynix joining the effort to some extent.\u00a0 And while serious investment in NIL came years too late, there is still a good chance they will succeed, at least for flash production.<\/p>\n Stochastic awareness<\/strong> seems to have hit critical mass this year.\u00a0 At the dimensions we are now experiencing, the fundamental stochastics of the world are coming to dominate lithographic behavior.\u00a0 Stochastics are hard to control, but any hope that we might do so will be through greater theoretical understanding and careful experimental measurements.<\/p>\n Trending Down:<\/strong><\/p>\n Directed self-assembly<\/strong> (DSA) progress has been disappointing in the last year, though that could be due to my inflated expectations.\u00a0 It appears that no one is yet using DSA in production, and every head-to-head with a competing method (atomic layer deposition for contact hole shrinks, SAQP for lines and spaces) has favored the incumbent process.<\/p>\n EUV resists<\/strong> switched from excitement about nanoparticle resists to excitement about metal-containing resists.\u00a0 There is much hope that real progress is just around the corner, but results remain depressingly consistent:\u00a0 the only way to lower LER is to raise the dose.\u00a0 Resist developers have not embraced a thorough understanding of stochastics as the foundation of their resist design, and have not internalized Lord Kelvin\u2019s dictum:\u00a0 if you can\u2019t model it, you don\u2019t understand it.<\/p>\n <\/p>\n Of course, there were many other things going on at the conference, and I was able to attend only a small fraction of the many talks presented this past week.\u00a0 As always, I am invigorated by the progress and learning that I have seen, and exhausted by the non-stop intellectual challenges that this symposium provides.\u00a0 When I hit that post button for this final summary, I\u2019m going to bed.<\/p>\n","protected":false},"excerpt":{"rendered":" I bounced all over the conference on Thursday (the last day), from Tim Brunner\u2019s paper predicting focus and overlay performance based on measured wafer bow and thickness, to Derk Brouns\u2019s update on an EUV pellicle.\u00a0 Nelson Felix of IBM discussed early use of EUV lithography for 10-nm and 7-nm node logic devices (as opposed to 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