{"id":768,"date":"2026-02-24T09:19:33","date_gmt":"2026-02-24T15:19:33","guid":{"rendered":"https:\/\/lithoguru.com\/life\/?p=768"},"modified":"2026-02-24T09:19:33","modified_gmt":"2026-02-24T15:19:33","slug":"spie-advanced-lithography-and-patterning-symposium-2026-day-1","status":"publish","type":"post","link":"https:\/\/lithoguru.com\/life\/?p=768","title":{"rendered":"SPIE Advanced Lithography and Patterning Symposium 2026 \u2013 day 1"},"content":{"rendered":"\n

The 51st<\/sup> SPIE lithography symposium in San Jose has grown from last year, with more the 2,500 attendees and 550 abstracts accepted.  At the plenary session Andreas Erdmann of the Fraunhofer Institute received the prestigious Frits Zernike Award in Microlithography for his important work in lithography simulation.  His many contributions to simulating 3D mask effects in Extreme Ultraviolet (EUV) lithography have been especially valuable.  Congratulations, Andreas!  We also saw three new SPIE Fellows being introduced:  Toshiro Itani, Frank Schellenberg, and Tadahiro Takigawa.<\/p>\n\n\n\n

The first plenary speaker was Unoh Kwon of SK hynix who talked about the importance of high bandwidth memory (HBM), especially DRAM, to the growth of artificial intelligence (AI).\u00a0 As he said, \u201cThe bottleneck of AI systems is shifting from compute to memory.\u201d\u00a0 Given how much money Nvidia has made from the compute side of AI, this is a welcome development for memory makers, who only a year ago were in a less desirable financial environment.\u00a0 As leading-edge memory makers shift to filling the HBM demand, the supply of all DRAM is falling behind demand with predictable results.\u00a0 (This is good for those DRAM makers; not so much for anyone who needs to buy memory of any kind.)\u00a0 Kwon\u2019s excellent talk described the AI need for high bandwidth (i.e., speed), high capacity, and low power, resulting in the use of wide I\/O channels, packaging memory close to the GPU, and stacking the DRAM chips higher using through-silicon vias (TSV).\u00a0 The latest HBM are stacking 16 DRAM chips in one package (still under 1 mm tall) to give up to 48 GB capacity, though power consumption is still too high.<\/p>\n\n\n\n

Hui Peng Koh, General Manager of Global Foundries\u2019 Fab 8 in Malta, NY, gave the second plenary talk on managing a high-mix, non-leading-edge foundry.  Global Foundries\u2019 profile was significantly raised during the pandemic when supply chain disruptions meant many customers (especially automakers) couldn\u2019t get enough chips.  As Koh said, \u201cSupply chains optimized globally for efficiency are not always resilient in the face of disruptions,\u201d which Global Foundries has sought to address by spreading fabs with redundant manufacturing capabilities throughout the world.  In a topic that is of great interest to me, she described how photonics chips, with relatively large feature sizes, demand extreme manufacturing precision.  Optical waveguides need very low line-edge roughness (LER) to prevent optical loss from scattering.  My favorite quote: \u201cLER is not just a metric \u2013 it\u2019s a performance limiter.\u201d<\/p>\n\n\n\n

At the metrology conference later in the morning there was a brief memorial to Alok Vaid who died in the past year (way too young), followed by a history of the conference on it\u2019s 40th<\/sup> anniversary.  And it was during this history overview that I was again reminded of the immense philosophical problem, studied as far back as the 13th<\/sup> century by Thomas Aquinas, called bilocation<\/em>:  you can\u2019t be in two places at the same time.  Before Nivea Schuch reached the fourth decade in her review of metrology milestones I had to leave for the resist conference in order to see Luciana Meli of IBM.  The expected transition from nanosheet transistors (used at the 3 or 2 nm nodes) to nanostack transistors (expected sometime below the 10A node) will be limited not as much by resolution as by edge placement error (EPE) control.  According to Meli, High-NA EUV lithography will provide some relief from the Stochastics Resolution Gap, but only for a while.  By the time we reach the nanostack transistor era we will be back to that ugly trade-off between stochastics errors (manifest as EPE) and exposure dose.<\/p>\n\n\n\n

Jumping again to the metrology conference, Steve McCandless of Micron talked about the use of AI and machine learning (ML) in metrology.  He assured the metrologists in the room that by reducing time to solution, \u201cAI [was] not here to take our jobs, but to free up our weekends.\u201d  (While I hope that is true in semiconductor manufacturing, I\u2019m sure it won\u2019t be true in many other professions.)  Most of the applications he described use ML\u2019s incredible ability to interpolate:  train a model with accurate metrology data (or simulation data) at various important conditions and let it fill in \u201cvirtual\u201d results easily and cheaply at others.  While many hope that AI can also do a good job of extrapolating, I have my doubts.  Even knowing when an AI result has been interpolated versus extrapolated can be difficult, which of course leads to the biggest roadblock to the widespread use of AI in metrology: trust.  Later that afternoon Danah Kim of Gauss Labs talked about their use of \u201cvirtual metrology\u201d for tool-to-tool matching, and \u201ctrust\u201d was the word that kept going through my mind.<\/p>\n\n\n\n

Towards the close of the day I was pleased to see extensive data on High-NA EUV single patterning of small tip-to-tip (T2T) dimensions.  From my experience, low-NA printing of 15 nm tip-to-tip CD at a tight pitch (28 nm) results in very high T2T local CD uniformity (LCDU) \u2013 between 6 and 8 nm.  That\u2019s a yield-limiting amount of variation.  Shruti Jambaldinni of Lam showed that High-NA EUV can print even smaller T2T CD at a pitch of 20 nm with LCDU between 3 and 4 nm.  She optimized their LAM dry resist absorption versus depth, plus illumination shape and mask absorber choice, to push the T2T LCDU down from 4 nm to 3 nm, though etch bias pushed that benefit to larger T2T CD.  The last talk of the day for me was by Yeongchan Cho of Samsung, describing the printing of square arrays of contact holes at the resolution limit of 0.33 NA EUV single printing.  These 30 nm pitch holes could only be printed using a clear-field mask and negative tone metal-oxide resist after extensive source-mask optimization.  I think there were some other tricks involved as well that Mr. Cho did not mention.<\/p>\n\n\n\n

The long first day of the symposium ended with a panel discussion commemorating its 50th<\/sup> anniversary.\u00a0 I was honored to be on the panel with Burn Lin, Martin van den Brink, Grant Willson, and Janice Golda as we talked about a few of the lessons learned during those exciting fifty years.\u00a0 Dan Hutcheson chaired the panel using a talk show-like interview mode that worked very well, soliciting a few of the many fascinating stories that all of us have in abundance.\u00a0 With a theme of \u201cmaking the impossible possible\u201d, it is clear that the next half-century of this conference will see many other \u201cimpossible\u201d challenges overcome.<\/p>\n\n\n\n

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The 51st SPIE lithography symposium in San Jose has grown from last year, with more the 2,500 attendees and 550 abstracts accepted.  At the plenary session Andreas Erdmann of the Fraunhofer Institute received the prestigious Frits Zernike Award in Microlithography for his important work in lithography simulation.  His many contributions to simulating 3D mask effects […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[2],"tags":[6],"class_list":["post-768","post","type-post","status-publish","format-standard","hentry","category-microlithography","tag-spie"],"_links":{"self":[{"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=\/wp\/v2\/posts\/768","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=768"}],"version-history":[{"count":1,"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=\/wp\/v2\/posts\/768\/revisions"}],"predecessor-version":[{"id":769,"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=\/wp\/v2\/posts\/768\/revisions\/769"}],"wp:attachment":[{"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=768"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=768"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/lithoguru.com\/life\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=768"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}