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San Jose, California, February 21– 25, 2010
(The following diary appeared first as a daily blog at http://life.lithoguru.com/ and is reproduced here in a slightly edited form.)
Day 0 – SPIE Advanced Lithography Symposium 2010
I’m back. It’s the end of February, so I must be back in San Jose for SPIE’s annual Advanced Lithography Symposium. I have mentally prepared myself for week of exhausting days standing and speaking and drinking, seeing numerous friends and colleagues, forgetting the names of people I should remember, getting excited by incredibly good papers and disgusted by incredibly bad ones, arguing about the future of various technologies and our industry, thrilling to the discovery of some new opportunity while mourning the loss of another. Each year this conference gives me something new to think about and look forward to for another year, each conference with its own personality and, eventually, its own memories.
First the numbers. Last year attendance was down 60% from 2008 (to about 1000), a dismal but not unexpected result given the economy and the state of the industry. This year it is up 25%, a big improvement but still a long way from its glory days. The most obvious manifestation of this new, smaller reality is the length of the conference – shortened by one day. I wonder how many people booked their plane tickets before realizing that there is nothing to stay for on Friday (like I almost did). Perhaps a more disturbing trend is the make-up rather than the number of people attending. Five years ago more than half the attendees were at this conference for the first time. This year, less than a quarter are newbies. Like me, the conference is getting grayer.
I started off the conference, like every year, by teaching a full-day short course on Sunday. The short courses have definitely suffered with the economy. Compared to four years ago, there are half the number of courses being offered and one fourth the number of course attendees. My course did better than most, with just under 20 students (and that despite the fact that it is more expensive than most, since I force the students to buy my textbook as a part of the course fee!).
The biggest change this year at the AL Symposium is the addition of a new conference – EUV Lithography. Splitting off from its old home in the emerging/alternative lithography conference, EUV is making a bold statement that it is now mainstream – it has emerged. Certainly the number of papers being presented gives credence to this strategy: about 150, more than any other conference at the symposium. Last year I famously predicted that the EUV lithography conference would be resounding success in 2010, before plummeting to zero papers in 2011. So far my prediction is right on target.
[OK, so maybe my prediction is a bit of an exaggeration. It might be 2012 before the number of EUV papers goes to zero.]
As a final note of introduction, as I approach the age of 50 I have become enamored with anniversaries, especially of the round number variety. I gave my first paper (on PROLITH) at this conference 25 years ago. I started FINLE Technologies a few weeks before SPIE 20 years ago (I also had my first bathtub party 20 years ago). And a few weeks before SPIE 10 years ago I sold FINLE to KLA-Tencor. I can’t help but notice that by the end of this week PROLITH will have been a part of KLA-Tencor for longer than it was a part of FINLE Technologies. Time moves forward, things change, life is different. I’m glad for that.
Day 1 - SPIE Advanced Lithography Symposium 2010
The first day of the symposium begins with the plenary session. I was excited to see Marc Levenson pick up the 7 th Frits Zernike Award for Microlithography. Very well deserved recognition for his work in phase-shifting masks and wavefront engineering. [A quick medal count - IBM and IBM alum have 4, the rest of the world 3.] Five new SPIE fellows were inducted as well: Bob Allen, Jos Benschop, Cliff Henderson, Soichi Owa, and Jim Potzick. Congratulations!
The three plenary talks were all solid, but none were stand-out. Ushida-san of Nikon gave the best talk, though it had the predictable sales pitch for Nikon’s newest immersion scanner. I liked the way his talk was peppered with Japanese sayings (“The priest who preaches foul doctrine shall be reborn as a fungus.”). Nikon is finally correcting the NA gap in 193 scanners, bringing their highest NA up to 1.35 to match ASML. And since Nikon has been understandably unwilling to bet their company on EUV, they outlined a strategy for pushing 193 with double patterning to 22-nm half-pitch and a little below, making the 16-nm half-pitch node (which is NOT the 16-nm node) a contest between EUV and quadruple patterning. Quadruple patterning? Really?
I find it very interesting to see various players in the industry slowly getting behind this basic double-patterning strategy: Designs are restricted to essentially one-dimensional features of a single pitch on a grid. The first patterning step uses 193i with sidewall-spacer pitch doubling that can get the final pitch down to around 38 – 40 nm. A second patterning step then cuts the lines to make the final pattern. The resolution of the second patterning step determines the tip-to-tip spacing of the line patterns, but is a secondary (though important) influencer of packing density. What tool will do the cutting? Immersion with all the optical tricks? Multiple e-beams? EUV? Yes, Intel has proposed that the proper role of EUV may be to do the cutting of fine patterns made by 193 immersion. We live in a funny world.
With the start of the conference sessions I went to the resist conference and saw the invited talks. I was surprised to see in the talks one picture of me and one picture of my Lotus (actually a stand-in picture – my Lotus is red). It’s important to have good jokes in an invited talk, I suppose. John Sturtevant of Mentor talked about the compute load for model-based OPC. At the 130-nm node one layer required model-based OPC, and that took about 200 CPU hours. At the 16-nm node, we expect 50 layers to need MBOPC and each of those require 200,000 CPU hours. That’s a hefty compute load. In the afternoon I saw a couple of resist papers on LER, but not much that made me sit up and take note.
All-in-all, the conference is off to a good start.
Day 2 - SPIE Advanced Lithography Symposium 2010
By Tuesday my focus has fully shifted to attending technical talks. This has gotten easier for me in the last few years since I am becoming less of a generalist and more of a specialist on line-edge roughness (LER). I search out all the LER papers first, and then find other interesting topics to listen too when there aren’t any LER papers to hear.
I started in the optical lithography session, with three very good invited talks. Prof. Zhang of Berkeley gave an informative talk on the hot science topics of super-lenses, plasmonic imaging, and negative refractive index metamaterials. Fascinating stuff, showing that looking at old physics in new ways can lead to very strange results. It’s funny, though, to watch someone from the science research community address lithography. They frequently talk about “breaking the classical resolution limit” with their new approach. Then, they either show an isolated feature (which has no classical resolution limit), or a dense feature with a classical pitch limit of wavelength/NA. When they show a (very poor) result with resolved features of half of this “classical limit” (typically hundreds of nanometers in size since they use i-line), there is much rejoicing in Nature or Science. Ahem, excuse me? Look at all the results at this conference where the pitch is near 0.5*wavelength/NA, the images are beautiful, and we can print 10 billion of them for a dollar! Claims of revolutions in lithography aside, the science is still very good. There was also a great paper on transistor architectures beyond the metal gate MOSFET, and Luigi Capodieci talked about kumbaya lithography (can’t we all just work together?). Luigi had some of the most insightful statements I’ve heard so far this week: “We often call ‘random’ what we can’t model”, and the subtle switch from thinking about controlling variability to managing (i.e., living with) variability. His attempt to coin “computational technology” as an extension of computation lithography that includes design optimization will, I suspect, fall flat.
There was an LER metrology session in the morning, but I didn’t see anything to make me think that LER metrology has improved in the last year. Scattered throughout the day there were various resist papers addressing LER (both 193 and EUV). There has been some progress in figuring out how to lower acid diffusion, but overall the best LER numbers reported don’t seem to have changed in the last year. For EUV resists, the consensus seems to be that we should work on resolution and sensitivity improvements, and hope that LER will work itself out by the time we get to manufacturing. Maybe some post-develop treatment (a magic rinse) will reduce LER and make the problem go away. Maybe we can find a rinse that will make our CD variations across the wafer go away, too.
At the poster session, the difference between this year and years past was manifest. The number of posters looked to be down by two-thirds, and one could easily wander around and find all the posters of interest, with plate of Mexican food in hand, in 30 minutes. I gave a poster and the number of people who meandered past was quite minimal.
Finally, after a full day of technical papers, there was the “trial”, a mock trial of EUV versus double patterning (Kafka would have been pleased). People have said it was fun for everyone, and I hear that consensus put the conclusion at a draw. But I just couldn’t go. I needed a beer and so I unwound at Gordon Biersch. A little rest and I’ll be ready to do it all again tomorrow.
Day 3 - SPIE Advanced Lithography Symposium 2010
Attending a meeting like Advanced Lithography I always have one hope: that I will listen to a paper that makes me say “wow!” After the first two days there were no “wow” moments. But then it happened for me on Wednesday. It was the first resist session in the morning, and I saw why Greg Wallraff and Bill Hinsberg’s group at IBM Almaden Research is so unique. Linda Sundberg gave a paper that I found hard to imagine coming from anyone else’s lab. The problem was an old one, though with a modern twist: how big an effect is developer depletion, and how can we separate that affect from chemical flare (acid that evaporates from one spot on the wafer and then redeposits nearby). What made the paper so good was the approach – she didn’t ask “what’s the easiest way to figure this out”, but asked “what’s the best way to figure this out.” They built a flow-cell to send a very controlled, small volume of developer sequentially across a line of exposed resist patterns to see how CD varied with order of contact with the developer. Sunberg happily described the early failures of this flow-cell, the redesigns that gradually improved it, and how the final version worked. It was a good idea followed by systematic attacks on the inevitable problems leading to an answer to a question that we’ve been asking in this industry for 20 years. Outstanding work.
There were also very good papers by Vivek Prabhu of NIST and Vassilios Constantoudis of Demokritos (Greece) in that same session. I walked out for the coffee break remembering why it was I love this conference. Later that morning I saw a good paper by Kedar Patel of SanDisk on comparing LWR measurements for different next generation lithography (NGL) approaches. His data was excellent, but his conclusion that every NGL approach can meet the ITRS roadmap specifications for LWR was inexplicable. I always enjoy discovering a new student, coming to the conference for the first time, who has become turned on by lithography. Alessandro Vaglio-Pret is getting his PhD at Imec and he gave a wonderful talk on roughness post-treatments, a topic many have discussed but only Alessandro provided reliable data for.
I gave a paper on my approach to modeling line-edge roughness in the afternoon (it’s always fun to give a talk), then finally gave up on attending papers for the rest of the day. I was winding down my brain and turning the conference into a social event (one of its other important uses). I talked to so many people at the poster session that I forgot to see any posters. I hit up a few hospitality suites in the evening, then went to bed thinking that this was a very good day.
Day 4 - SPIE Advanced Lithography Symposium 2010
The “hottest ticket” of the week were the ASML and Cymer updates on EUV lithography progress. It was beyond standing room only for the ASML talk, with a line out the door of the conference room. I decided not to brave the crowds, since I knew what was going to be said: everything is going even better than expected; the project is on-time and according to plan; EUV is inevitable. I poked my head in for the Cymer update on building sources for the ASML preproduction tool (PPT). They have six sources under construction, but unfortunately they will ship with an expected output of 40W, 20% of the 200W required for the PPT to have a chance of meeting its 60 wafer per hour throughput goal. They plan to upgrade the source in the field in two steps, first to 90W and then to the final 200W. Challenging, to say the least. Of the three technologies that could easily kill EUV lithography, source power is the most obvious and thus will probably get blamed when EUV dies (the other two problems are resist performance and mask defectivity, both of which will also take much longer to solve than the industry’s timetable demands).
As I come to the end of the week, I start thinking of summing up my impressions of another Advanced Lithography Symposium. I attended only about 20% of the 340 oral papers presented this year, so my sampling is certainly far from comprehensive. Hopefully, though, my posts this week have given an accurate impression of the conference nonetheless. Several people mentioned to me that they were impressed with the progress being made on directed self-assembly polymers – it’s moving beyond a science project to become an engineering project, and the results are looking good.
Since I have complained repeatedly in past years about lying with graphs (no numerical labels, misleading axes ranges that hide variations, etc.), I seem to have created an informal graph-police among my fellow lithographers who alert me to what they consider to be the most egregious abuses. One new complaint: displaying two wafer maps and then claiming that the spatial signatures are correlated because they look similar. But why do ‘chi-by-eye’ when performing a real correlation, with a scatterplot and a correlation coefficient, is trivial to do? Is there something to hide, or is the author just being lazy?
Finally, here are some of my favorite quotes from the conference. First, the bar quotes – gems from lithographers with a beer in their hand:
“You spend $120M on an EUV scanner. The result? You get a space with three more photons than a line.” (From an engineer worried about line-edge roughness.)
“I just spent 18 hours exposing one sh!$ty wafer with EUV.” (A student talking about collecting experimental data on the ASML ADT.)
And finally, quoting myself speaking directly to the audience during my line-edge roughness talk: “Your LER metrology sucks.”
And so ends another intensive week of talking, thinking and drinking about lithography. I love this conference!
Chris Mack is a writer and lithographer in Austin, Texas.
© Copyright 2010, Chris Mack.Diaries from other lithography conferences...