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San Jose, California, February 24 – March 1, 2013
(The following diary appeared first as a daily blog at http://life.lithoguru.com/ and is reproduced here in a slightly edited form.)
Advanced Lithography 2013 – A Prologue
Welcome to San Jose and the beginning of the Advanced Lithography Symposium. The last year seemed to zip by in hurry, and it was an interesting one. The lithography year 2012 was dominated by two big stories: progress in directed self assembly (DSA) and lack of progress in Extreme Ultraviolet (EUV) lithography. I’m anxious to hear the progress reports for each this week. For EUV, delays in the growth of source power are on everyone’s mind, but I’d like to point out that progress in the other essential areas of development are also under pressure. We are still mostly blind when trying to assess the defectivity of EUV reticles compared to spec, and resist line-edge roughness (and the CD Uniformity loss caused by it) is barely budging. Every year that EUV is delayed means that these specs must scale with the new resolution goal (will EUV be ready for the 8/7-nm node?), and we are still not sure if the 22-nm node specs can be met.
The conference this year is certainly on track to be a success. The attendance looks to be about the same as last year (1500 paid attendees, 2300 including exhibitors and exhibit-only attendees). The biggest conference this year is the Metrology conference (122 papers), and the smallest is the Design for Manufacturing (DFM) conference (25 papers). I’m giving the keynote for the DFM conference on Wednesday, so even though it is small, please don’t miss it!
On a personal note, this month marks my thirtieth anniversary as a lithographer. Am I really that old? When I glance in the mirror, or get up with a sore back after too many hours in a conference chair, the answer seems depressingly clear. But when I think about how much fun I am having in the world of lithography I somehow don’t feel that old. I guess that is what really counts. And this week will certainly be great fun. Let the conference begin!
SPIE Advanced Lithography 2013 – day 1
Day 1 of the SPIE Advanced Lithography Symposium began, as always, with the plenary session. Bill Arnold, former lithography manager at AMD and now CTO at ASML, gave a “state of the union” address – he is this year’s SPIE president. (Congratulations, Bill – I voted for you!) The 10 th Zernike Award for achievements in microlithography went to Dave Markle, a well-deserved honor (full disclosure: I nominated Dave, so my opinion may be biased). And SPIE inducted some of its newest members into the ranks of SPIE Fellow: Yan Borodovsky of Intel, Alain Diebold of the University of Albany, Kafai Lai of IBM, Bryan Rice of SEMATECH North (is there a SEMATECH south?), and Martin Richardson of the University of Central Florida. Congratulations to all.
The first plenary talk was by Bill Siegle on a topic very dear to me – the history of lithography. Bill spent many years at IBM and AMD, and keeps his hands in the industry as a member of the ASML board of advisors. (I was glad to see that he kept his ASML promotion to a bare minimum – only a couple of slides.) I especially liked his description of an internal step-and-repeat tool development project at IBM in the early 70s – the 5XLFS. It was a “dismal failure” and “generated a lot of scrap”. The industry was finally reaching the point where process equipment was best supplied externally rather than internally. The first commercial stepper, the GCA DSW 4800, could “predict the weather” due to its high sensitivity to barometric pressure. He provided many good lessons from this history, but I like #6 best: It’s impossible to predict 10 years ahead. I agree, but somehow it doesn’t stop me from trying.
Howard Ko of Synopsys gave a benign talk on the evolution of EDA (electronic design automation), and Chuck Szmanda gave an interesting talk on patent law (cheers to the selection committee for picking an unconventional plenary topic).
By 11am the technical sessions had begun. I went to see my good friend Mark Smith give a great talk (yes, I am biased) with an even better title: “Optimization of a Virtual EUV Photoresist”. There are so many ways to play on that title, but I’ll just say that I love virtual photoresists. They don’t smell.
The most important talk of the day (IMHO) was given by Sam Sivakumar of Intel. He presented results on working 22-nm SRAM devices (the first?) manufactured with EUV on the NXE:3100. EUV was used on two levels (a “line-like” layer and a “hole-like” layer, whatever that means) and the manufacturing performance of the 22-nm SRAM test vehicle was compared to standard 193-nm manufacturing. The devices worked well (though I didn’t understand the meaning of the device characteristics plots that he presented, since they had no axes labels), and this was an important milestone. Of course, the throughput was extremely low, but the point of the exercise was to test everything else about the manufacturing readiness of EUV. Wafer defect was only about 10 – 20X higher than the mature 193-nm process (not unexpected at this stage of development), and no killer mask defects were present. Sam showed a slide that said one undetected adder defect on the reticle could cost Intel $5M/day, so this is important. Overall, Intel seemed happy with the results.
But let’s keep things in perspective. This is a 22-nm SRAM test vehicle, which for Intel means the gate level is at a 90-nm pitch. Thus, the device is not sensitive to reticle defects that are beyond today’s inspection sensitivity but will be critical before EUV goes into production. Further, this test does not stress the EUV RLS triangle of death (the ugly trade-off between Resolution, Line-edge roughness, and Sensitivity that currently would kill any hope of economic manufacturing with EUV). This work had to happen, and I applaud Intel for publishing it (I hope Samsung and the other NXE:3100 owners will do the same). But it is not an existence proof for the manufacturability of EUV “if only we had a source”. It will take much more.
For the rest of the day I hopped from room to room trying to learn everything I could about line-edge roughness (LER)/linewidth roughness (LWR). I am happy to see that there are many more papers on that topic this year. On this first day the emphasis of most of them seemed to be on the importance of post-processing for LWR reduction. But here is my dilemma: 1) low-frequency LER causes an increase in CD non-uniformity, especially for contacts but for short-width gates as well; 2) this problem will be devastating to EUV lithography if low-frequency LER isn’t reduced significantly; and 3) LER post-processing won’t help with this problem since it does not (cannot) reduce low-frequency LER. Point #3 is where there may be some controversy (meaning that not everyone has come to see things my way). So here is my challenge to all those promoting the use of LER post-processing: prove to me that I am wrong by either convincing experimental evidence that low-frequency LER is reduced or a convincing proposed mechanism, and preferably both. Actually, I need both, and I haven’t seen it yet.
Finally, a soap-box moment (something that many of you know I am fond of). When is it OK to describe your idea as “new” when giving a paper? Here is a new theory, a new mechanism, a new approach, a new design. My advice: probably never. If your idea is truly new, then astute attendees of your talk will realize it. It’s OK to tell them why the problem you are working on is important, or why a solution to that problem is important. But don’t tell then that your work is important – that is a judgment they should make for themselves. I know that this advice is opposed to what every marketing professional will tell you, but we are not marketing people, we are scientists and engineers. And besides embracing the important ethic of humility, it is much safer not to claim that your idea is new for the simple reason that it probably isn’t. There is very little new under the sun, even though novelty is what advances science and why we are all at conferences like this one. None of us are familiar with everything in the literature, and an explicit claim of novelty can result in a swift rebuttal by someone pulling out an obscure (or not so obscure) reference to prove you wrong. Let the audience judge the novelty of your idea, and when you’re confronted with an old reference that did the same thing as you, you can be happy for the education and the knowledge that someone else has validated your idea.
SPIE Advanced Lithography 2013 – day 2
There were some great papers at AL on Tuesday. Here are some of my favorites. Peter Trefonas of Dow created a photosensitive block copolymer using a class of molecules called bottle brush polymers. This very early work nonetheless exhibited very good results – close to 20 nm resolution (e-beam litho) with nearly the first bottle of stuff they mixed up. The idea is simple: marry the high resolution and high sensitivity of chemically amplified photoresists with the low line-edge roughness and good CD uniformity of self-assembled block copolymers. Cool. And it looked like great fun for the chemists.
Julius Santillan of the EUVL Infrastructure Development Corp in Japan wowed the metrology conference with a high-speed atomic force microscope (AFM) that could measure 32-nm line/space features in situ during development using a carbon nanotube fiber cantilever in tapping mode. With a scan time of 2 seconds (faster is possible, he says) for a pixel size of 2.5 nm and an area of 1000nm X 750 nm, the tool made absolutely remarkable movies showing resist development and roughness formation in several different kinds of resists. The difference between PHS-based EUV resists and methacryl-based EUV resists was startling. The impact of resist development on LER was clear for all to see. Now the challenge is how best to use this new view into the physics of LER formation.
The progress in directed self-assembly (DSA) since last year has been remarkable, as evidence by the number of papers on the topic this year if nothing else. The science is advancing, the technology is advancing, and the practice is advancing. We can make very tight pitch lines and spaces with DSA, but how can we cut them to make circuit patterns? Why, with DSA of course! Even better than small lines and spaces, DSA is good at making small contact holes (though not on a super-tight pitch). So the topic that most caught my attention today was the idea of using DSA-shrunk contact holes to the cut the DSA lines. The 14/10nm node(s) could be made with two 193i patterning steps (and thus only two masks), but with significant design/layout impact. This is a very, very interesting approach. I think we will hear much more about this in the next year.
As the afternoon turned to evening I went from a panel discussion on DSA to the poster session, with a “super panel” pulling in all the conferences still in store. But when the good beer ran out at the poster session, I took the opportunity to retire for the evening and let Aki Fujimura buy me an expensive dinner (thank you, Aki!). And there is still that pesky business of getting my talks ready for Wednesday. Yes, this is life at the Advanced Lithography Symposium.
SPIE Advanced Lithography 2013 – day 3
Wednesday was, for me, a busy day since I had two talks to give. The first was the opening keynote talk at the Design for Manufacturability (DFM) conference entitled “The future of lithography and its impact on design”. The take-home message was that lithography would become less critical to the success of the industry, and that materials, device architecture, and design would be the key technologies of the future. You can find the presentation here. Afterwards I was surprised when a few people told me they found my presentation depressing or that they were now polishing up their resumes and thinking about a future career in design.
I saw a few updates on Mapper technology, that massively parallel e-beam technique that, if it works, could provide an important solution for complimentary lithography, especially in the foundry business. Unfortunately, their first pre-production system, the Matrix 1.1, won’t ship till the second half of this year. That tool will have over 1,000 beams and run at 1 wafer per hour (as opposed to the 0.002 wph throughput of the current demonstration system). As with EUV, getting tools with sufficient throughput to enable development is a critical milestone.
I attended a few talks on metrology and resist materials related to line-edge roughness (LER). They reported small progress, but nothing even close to a breakthrough in either understanding or performance. LER remains a tough nut to crack.
With several sessions, about 70 papers, a panel, and a short course devoted to directed self assembly (DSA), this topic has definitely turned a corner at the conference. But with success comes an inevitable problem: commercial papers. I heard many complaints from people about papers describing the benefits of “polymer A” over “polymer B”, graphs with no axes numbers, and papers meant to impress rather than inform. It is certainly a high price of success to trade integrity for profit.
SPIE Advanced Lithography 2013 – day 4
The final day of the Advanced Lithography Symposium contains what is commonly referred to as the “tool” sessions, where tool makers give updates on their latest and greatest products. As such it tends to have the most commercial presentations, with all the problems that come with commercial pressures. For the EUV conference it is also the day where technology cheerleading, and skepticism, reaches a fevered pitch.
ASML described the status of their production EUV scanner, the NXE:3300B. Eleven systems are under construction, nine of which should ship to customers by the end of this year or early next year. These systems will ship regardless of the source power available, and so the most anticipated talk was given at 9am by Cymer. To put this year’s report in perspective, one year ago Cymer was delivering a 9W (intermediate focus) EUV source to customers, claiming that a 20W source was about to be “available”, and predicting 100W by December 2012. The goal for production remains 250W. This year Cymer was “proud” to demonstrate 40W production-like performance and said sources for the 3300 had already been shipped to ASML. Let’s parse this announcement a bit.
What Cymer showed was a modified 3100 source that achieved 40W production-like performance for 6 hours one day last week, and 40W production-like performance for 6 hours one day this week. While a definite milestone, it is certainly not the same as delivering 40W performance to a customer for regular production-like use. So, in the last 12 months Cymer has doubled source power in the lab. In six months ASML will begin shipping tools with, they hope, an 80W source attached. I find it highly unlikely that this will be achieved. An 80W source should enable about 40 wafer-per-hour throughput or so, which will be fast enough to enable valuable production learning. Then Cymer will need to increase source power to 140W (and deliver that power to customers) by the end of 2014 to meet ASML’s stated goal of having EUV lithography that is producing chips at 70 wph by the end of 2014. Cymer has to beat Moore’s Law by a long shot, doubling source power twice in the next 18 months. That will be a hard job, indeed.
Next, Zeiss showed their progress and roadmap for EUV optical systems. An important question is how high can the NA go before two more mirrors are added (thus cutting the throughput in half). Their answer: 0.45. Since the NXE:3300 has an NA of 0.33, increasing the NA to 0.45 will allow the resolution to improve by a factor of about 0.73, close enough to the expected feature size reduction of 0.7 that a second generation of EUV production tools might take the technology to one more node. With off-axis illumination (and a low k1), 10-nm or 11-nm half-pitch might be possible with NA = 0.45. It will not be easy, though.
In the afternoon, the tool talks in the optical lithography conference touched on one of my pet peeves (some people claim I have too many pet peeves), so it is time to step up on the soap box again and talk about “lying with graphs”. There are many ways to lie with graphs, and most result from the practice of advocacy speech: using a graph to impress rather than inform. This is what marketing folks often do. It is not what scientists should do. Let me take as an example the topic of global warming. Hopefully everyone has seen plots of global surface temperatures that show a fairly steep rise over the last 50 years (close to 1 degree Centigrade). Now suppose you want to argue that global temperatures are not rising. One approach would be to plot the same data on a graph that has a y-axis origin of zero centigrade (or better yet, zero Kelvin). The result will be a trend that looks almost totally flat, since the variation will be hard to notice when squeezed into a few percent of the area of the graph. This technique works well whenever you want to show a flat trend in the data , regardless of the actual trend in the data.
The two laser talks, by Gigaphoton and Cymer, each displayed dozens of graphs that lie in exactly this way. Both lasers can control dose by pulse over time to within 0.2%. But to plot the data, they chose a y-axis that went from -1% to +1%, so that 80% of the y-axis range was unused. Wavelength stability, spectral bandwidth, beam position, beam profile size, divergence, and other laser metrics were plotted in the same way, sometimes using less than 10% of the y-axis range. Why even show the data if you purposely choose a y-axis that makes any data variation invisible? Obviously it is not to inform the audience. I’ve seen other talks over the years doing the same thing: wafer chuck temperature, aberrations across a slit, etc. There is a simple rule to prevent this: your data should use up 70% of the range of both the x- and y-axes. Don’t be caught lying with graphs.
And so ends another SPIE Advanced Lithography Symposium. 2012 was an interesting year in lithography. 2013 will be even more so.
Chris Mack is a writer and lithographer in Austin, Texas.
© Copyright 2013, Chris Mack.Diaries from other lithography conferences...