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Glossary of Lithography Terms - M


Mask A glass or quartz plate containing information (encoded as a variation in transmittance and/or phase) about the features to be printed. Also called a photomask or a reticle. (Historically, a photomask was the 1 X mask used in contact or proximity printing, whereas the reticle was a higher magnification version of a single field used to make the photomask. Today, the terms photomask and reticle are used interchangeably for all masks used in optical lithography.)

Example: Reduction projection printing significantly eases the burden of producing an acceptable mask compared to 1 X lithography.


Mask Aligner A tool that aligns a photomask to a resist-coated wafer and then exposes the pattern of the photomask into the resist.

Example: The far superior throughput of mask aligners over direct-write lithography tools has made them the tools of choice for semiconductor manufacturing.


Mask Biasing The process of changing the size or shape of the mask feature in order for the printed feature size to more closely match the nominal or desired feature size.

Example: Although mask biasing complicates the design and mask-making process, the improvement in linewidth control that results could well be worth the effort.


Mask Blank A blank mask substrate (e.g., quartz) coated with an absorber (e.g., chrome), and sometimes with resist, and used to make a mask.

Example: The use of attenuated phase shifting masks greatly increases the cost of the mask blank.


Mask Error Enhancement Factor The incremental change in the final resist feature size per unit change in the corresponding mask feature size (where the mask dimension is scaled to wafer size by the reduction ratio of the imaging tool). Abbreviated MEEF or MEF, a value of 1 implies a linear imaging of mask features to the wafer. Also called Mask Error Factor.

Example: Although a linear imaging system produces a mask error enhancement factor of 1.0 , near the resolution limit the MEEF often rises dramatically.


Mask Error Factor see Mask Error Enhancement Factor


Maskless Lithography Any one of a number of lithographic techniques (including direct-write lithography and programmable multimirror masks) that does not use a permanent, fixed mask to perform imaging.

Example: For low-volume IC manufacturing , maskless lithography could offer a compelling cost of ownership advantage.


Mask Linearity The relationship of printed resist feature width to mask feature width for a given process.

Example: Mask linearity is often used as a measure of the practical resolution of a process.


Mercury Arc Lamp A common light source used in lithographic exposure systems that produces intense radiation at the g-line, h-line, and i-lines of the mercury spectrum.

Example: The mercury arc lamp is the most common light source for optical lithography when the required resolution is greater than about 300 nm.


MEEF see Mask Error Enhancement Factor


MEF see Mask Error Enhancement Factor


Metrology The process of measuring structures on the wafer, such as the width of a printed resist feature or the overlay between two printed patterns.

Example: Determination of practical linewidth control requirements must include metrology errors as well as process errors.


Microlithography Lithography involving the printing of very small features, typically on the order of micrometers or below in size.

Example: Microlithography techniques are used extensively in semiconductor manufacturing as well as in compact disc mastering, thin-film head production, and many other advanced technologies.


Mix-and-Match Lithography A lithographic strategy whereby different types of lithographic imaging tools are used to print different layers of a given device.

Example: The use of mix-and-match lithography allows for reduced equipment and process costs at the expense of more complicated overlay requirements.


Model-Based OPC An optical proximity correction technique that determines the level of correction (how much to move a design feature’s edge) by iteratively simulating the lithographic result until the corrected design produces the desired resist pattern shape to within a preset tolerance.

Example: At the 130-nm technology node, most semiconductor companies switch from using rule-based OPC to the more robust and accurate model-based OPC.


Modeling see Simulation


Moore’s Law Named for Gordon Moore, one of the founders of Fairchild Semiconductor and Intel, the observation that the number of transistors on a typical chip doubles about 1 -2 years. In lithography, this law has come to describe the exponential decrease in critical dimensions used in IC manufacturing over time.

Example: By assuming that Moore ’s Law will continue to hold in the future, lithographic requirements can be predicted.


Multilayer Resist (MLR) A resist scheme by which the resist is made up of more than one layer, typically a thick conformal bottom layer under a thin imaging layer, possibly with a barrier layer in between.

Example: The need for a very thin imaging layer can be met using a multilayer resist scheme.