An excuse to travel to Hawaii? You don’t have to ask me twice. Especially if it is the Big Island, my favorite of the Hawaiian isles. My excuse this time? The 3-beams conference, also called triple-beams, EIPBN, or occasionally (rarely) the International Conference on Electron, Ion and Photon Beam Technology & Nanofabrication.

The conference was held last week (May 29 – June 1) at the excessively large Hilton Waikoloa Resort, where if I chose not to take the train or the boat from the lobby to my room, I could make the 15 minute walk instead. With the ocean, a lagoon full of sea turtles, dolphins to wonder over, and too many pools to count, one could easily spend a week’s vacation here without ever leaving the resort – which is no way to spend a vacation on the Big Island.

But I wasn’t here on vacation! I was here on business. OK, the conference was three days and I stayed for eight, but seriously, I was here for the conference. And so I diligently attended papers, ignoring the texts from my wife telling me which pool she was going to next.

Things began on Wednesday with the three plenary talks. Only later did it occur to me that they were of a common theme: optical lithography as the engine of scaling is reaching its nadir, so what will come next? Burn Lin, lithography legend and VP of TSMC, gave his now-familiar pitch for massively parallel e-beam direct write on wafer. His analysis is always insightful, but because development of a practical e-beam solution is still 5 years away (I’m being optimistic here), there was an all-too-common bias in his thinking: the devil we don’t know (e-beam) is better than the devil we do know (EUV). Since Extreme Ultraviolet lithography is at the end of its 20 year development cycle, we know all about the problems that could still kill the program. Since massively parallel e-beam wafer lithography is far behind, it is likely that we haven’t seen the worst problems yet (how bad will overlay be, for example?). And in fact, some problems are the same, such as line-edge roughness limiting the practical sensitivity of any resist system.

Matt Nowak of Qualcomm gave a great review of 3D integration through chip stacking. If Nvidia and Broadcom are right and litho scaling below 22-nm doesn’t yield either better-performing or lower-cost transistors, what is next? Innovations in packaging. While not as sexy as wafer processing, packaging adds a lot to the cost of an IC. And with 3D chip stacking, it is likely that packing costs would go down, system performance would go up, and we even might be able to lower wafer costs by better dividing up functionality between chips. It won’t be long before 3D integration is the new standard of system (chip) integration.

Finally, Mark Pinto of Applied Materials showed a very different example of what to do when silicon scaling begins to fail: go into another market. In this case, the market is silicon photovoltaics (PV). Historically, the PV market’s version of Moore’s Law has shown a 20% decline in cost/Watt for every doubling in installed capacity. That trend seems to be accelerating of late, with commercial installations now running at under $1/W. Grid parity, where the cost of solar electricity equals or is less than the market cost of electricity, has been reached in Hawaii and in several countries (even without accounting for the cost of carbon). The trends all look good, and solar is a good market for Applied.

After the plenary, it was off to the regular papers, with their interesting mix of the practical and the far out. First, an update on what I heard about EUV.

Imec has been running an ASML NXE:3100 for a year now, and its higher throughput means that process development is much easier compared to the days of the old alpha demo tool (ADT). Still, “higher throughput” is a relative term. The most wafers that Imec has run through their 3100 continuously is one lot – 23 wafers – taking about five hours. Thirteen minutes per wafer is a big improvement over several hours per wafer, but still far from adequate.

In the hallways, I heard complaints about $150,000 per EUV mask, and EUV resist at $40K per gallon. Everyone expects these prices to go down when (or if) EUV moves into high volume manufacturing, but anyone who thinks that EUV resists or masks will ever be cheaper than 193 resists or masks just isn’t thinking well. EUV may be Extreme, but it is also Expensive.

There were many excellent papers this year. JSR gave a great talk on some fundamental studies of line-edge roughness (LER) in EUV resists, developing some experimental techniques that were fabulous. A talk from the University of Houston explored the use of small-angle X-ray scattering to measure latent images in chemically amplified resists. Although promising, this techniques will need massive control and characterization to yield quantitative results.

Paul Petric of KLA-Tencor described progress on their e-beam lithography tool, REBL. We still have two years before an alpha tool might be ready to ship to a customer. Richard Blaikie from New Zealand gave a great talk on evanescent interference lithography, though I might be biased in my opinion since I was a co-author.

I had a few hallway conversations with folks about scaling. The economic barrier of double patterning means that pitch has stopped scaling for some levels. Metal 1, in particular, is stuck at an 80-nm pitch (it looks like for three nodes now), the smallest that 193 immersion can print in a single pattern. It seems likely that double patterning will have to be used at Metal 1 for the 14-nm node to bring the pitch down to 64 nm. The fin pitch for finFETs must scale, so self-aligned double patterning (SADP) is being used at the 22-nm node, but what will happen when the double patterning pitch limit of 40 nm is reached? The economics of litho scaling looks very ugly for the next few years, with a very real possibility that we just won’t do it (or maybe no one but Intel will do it).

On the last day of the conference there a slew of good papers on directed self-assembly (DSA), the hottest topic in the lithography world right now. Progress towards practicality is rapid, and universities continue to churn out interesting variations. IBM discussed the possibility of using DSA for fin patterning below 40-nm pitch. They seem very serious about this approach.

Some of my favorite quotes of the week:

Referring to the molten tin sources used for EUV, Jim Thackeray of Dow said “If nature can do volcanos, maybe we can do EUV.”
Referring to EUV resists that can also be used for e-beam lithography, Michael Guillorn of IBM said “In my opinion, this is the best thing we got from the EUV program.”
Referring to problems making the DPG chip at the heart of the REBL system, Paul Petric of KLA-Tencor said “Making tools for making chips is easier than making chips.”

It was a good conference and a fun trip, and now I’m back home, but many of my fellow conference attendees are not. Vivek Bakshi’s EUV workshop was this week in Maui, and next week is the VLSI Technology and Circuits Symposium in Honolulu. I know several folks were able to convince their bosses that a three-week, three-island business trip was required. At the VLSI symposium, one of the evening rump sessions is entitled “Patterning in a non-planar world – EUV, DW or tricky-193?” Patterning is on everyone’s mind now, even chip designers’. So much attention is generally not a good thing. But us lithographers can expect even more attention over the next 12 months, as the industry makes some of the most difficult choices it has ever made in its 50 year history.

While I was at the SPIE Advanced Lithography Symposium 2012 in February, SPIE videotaped a short interview for their SPIE.tv site. Here is a link, where I ramble on about Next Generation Lithography.

http://spie.org/x86784.xml

Moore’s Law has always been about economics: if we follow the trend of Moore’s Law, we can reduce the cost per function for our integrated circuits, making chips more powerful for the same cost, or making chips of a given capability cheaper. Historically, cost per function has decreased by about 29% per year, corresponding to a factor of 2 decrease in cost every two years. There are signs that this historic cost reduction trend will slow down. How much of a slowdown can our industry tolerate? If the cost per function is expected to decrease by less than 10% per year going forward, it is unlikely that chipmakers will be willing to invest the massive amounts required for a new generation of fabs. I suspect that the minimum cost per function decrease we can live with is about 15% per year.

What does this say about lithography costs and capabilities per technology node? The cost/function of a chip is the ratio of the cost/area of finished silicon from making the chip and the functions/area that the technology node can deliver. Over the last decade we have been on a 2-year technology shrink schedule, so that the functions/area double every two years. Thus, by keeping the cost/area constant, we have been able to reduce cost/function by 29% per year. If we stay on the same 2-year shrink cycle, a minimum allowed 15% cost/function decrease per year would allow a maximum of 20% increase in the cost/area of silicon each year. Alternately, if we keep the cost/area of silicon constant, we could slow down the 2-year technology node shrink cycle to 4 years between technology nodes, and still get the required 15% reduction in cost/function per year.

Of course, everyone in the semiconductor industry would love to stay on our historic trends: constant cost/area of finished silicon, and a two year cycle of doubling the functions/area. It seems unlikely that this trend can be maintained during the current decade, however. Thus, using a minimum allowed cost/function decrease of 15%/year as a target, we can either allow chipmaking costs/area to increase by 20% each year and stay on the 2-year technology node cycle, or we can allow our technology node cycle to slow to every four years while keeping manufacturing costs/area constant. Either option will allow for continued success, and probably a bit of growth, for the semiconductor industry. But if the technology shrinks come too slowly, or costs rise too quickly, the days of Moore’s Law will be numbered.

As expected, the first EUV session of the last day of the conference filled a large room. It was time to hear the status of EUV tool development, in particular the EUV sources. ASML started things off with a rosy recounting of the successes of 2011. After installing their sixth NXE:3100 preproduction tool, ASML bragged of the 5300 EUV wafers processed at customer sites by these six tools in 2011. I couldn’t help remembering the ASML press release from last month saying a single 193i tool processed 4000 wafers in a day. That, in a nutshell, is the gap between preproduction and high volume manufacturing. They have a long way to go.

The EUV source status reports made future progress to higher power sound inevitable. Today, customers have sources with 9W of power at the intermediate focal plane, a 20W upgrade is being qualified, 50W has been demonstrated, and getting to 100W by the end of the year is straightforward. What could be easier? Somehow, I remain skeptical. Maybe it is because neither source presentation mentioned the damage caused by tin debris – the 5kV shorts or the frequent replacements of $1M collector mirrors – which can only get worse as source power goes up. Maybe it is because the roadmaps made the optimistic assumption that doubling the input laser power would double the EUV source output. Maybe it is because every past source milestone has been missed and it seems likely that future progress will be harder than past progress. Maybe it is because nature does not like EUV.

Or maybe I am biased. I wish the source vendors luck in reaching their goals. They are under a lot of pressure. In contrast, there was frequent mention of significant progress in EUV photoresists. A demonstration of 16 nm lines and spaces looked promising, though the dose was 33 mJ/cm2 (most people are hoping for 20 mJ/cm2 eventually) and the LWR was 3.7 nm, 23% of the nominal CD. This is progress certainly, but I find it very hard to believe that both dose and LWR will be appreciably reduced by next year.

I enjoyed the session on roll-to-roll printing, especially the Rolith presentation on a cylindrical phase-shifting mask with a UV lamp inside. This world of super-high volume patterning on continuous rolls of low-cost substrates is so different from what I think of as lithography that I could do nothing but look on in amazement.

The day ended for me with the last optical lithography session, where Nikon and ASML presented the current status of the latest 193-nm scanners. While single-patterning resolution remains fixed, the rest of the tool is getting better: CD uniformity, overlay and throughput. Under ideal conditions, CD uniformity can be less than 1 nm, single machine overlay can be less than 2 nm, and throughput can be over 220 wafers per hour (with a roadmap to >270 wph). These tools are becoming optimized for double patterning.

My favorite quote of the day: “Math works.” – John Biafore, commenting on a presentation showing a successful simulation prediction.

My least favorite quote: Cymer, talking about their improved internal EUV source testing facilities, said they will “hopefully learn faster than [the chip companies] do.”

And so another SPIE Advanced Lithography symposium is over. Till next year.