SPIE Advanced Lithography and Patterning Symposium 2024 – day 2

The plenary session was split into two days this year, with two plenaries on Tuesday morning.  Ann Kelleher of Intel talked about her view of the new era of Moore’s Law: system technology co-optimization (STCO).  This is in addition to, not replacing, the prior eras of geometric scaling and design technology co-optimization (DTCO).  The new Moore’s Law metric is not the number of transistors on a chip, but the number of transistors in a package, with a goal of one trillion by 2030.  Some quotes from her presentation that stood out for me:

“DSA (directed self-assembly) is a key innovation that needs to be brought to high volume manufacturing.”

“The line between silicon and advanced packaging is blurring.”

Intel has been promoting their catch-up plan for close to two years now – five nodes in five years, culminating in the Intel 14A node, before starting back to a more relaxed two-year cadence.  But interestingly, the 14A node is expected to have a transistor density that is only 1.2X the 18A node.  In the past we might have called that a half-node, or even a shrink version of the existing node.  But maybe this is the new normal – smaller node-over-node improvements.

Chan Hwang of Samsung gave a plenary on lithography for memory production.  He spoke about many things that are front and center in my mind, especially contact hole edge placement error (EPE) and one of its largest components, local critical dimension uniformity (LCDU).  For EUV, the key to success is controlling LCDU at low dose.  Since the knobs for lowering stochastic LCDU are limited, their focus is on reducing global CDU to give more budget for LCDU.

Later in the morning there were several papers on a topic that has been bedeviling EUV lithography for some time:  image fading due to mask 3D effects.  For the case of dipole illumination (needed for the tightest pitches), the mask 3D effect causes a phase shift between the two diffraction orders, which results in an image shift.  Since the right pole shifts the vertical lines in one direction and the left pole shifts them in the oppositive direction, the result is an unshifted image with lower contrast and image log-slope.  The best long-term solution is to lower the mask 3D effects using new mask absorber materials, but that is still some years away.  In the meantime, Eelco van Setten of ASML described details of one proposal to add aberrations to compensate for this phase shift.  Of course, this makes many people nervous (we’ve been working on lowering aberrations for decades), especially since most masks include both tight-pitch lines and spaces plus other patterns that would be harmed by such aberrations.  Jieun Song of Samsung used a more traditional approach – source mask optimization (SMO), this time for staggered arrays of holes with the goal of reducing LCDU.  I have to admit, though, that this has a similar downside of being ideal only for the tight pitch holes and not for the other patterns on the mask.

Emily Gallagher ended the morning in the Optical and EUV Nanolithography conference with a talk about how mask roughness transfers to the wafer.  This topic has been around for many years (I wrote my first paper on it in 2009), but imec has taken a novel approach.  They programmed “random” roughness on the mask (not square waves of different amplitudes and periods that others have done in the past).  Jogs of various lengths and widths allowed control of both the mask LER and its correlation length.  Both the mask and the wafer printed with it were then measured.  I look forward to studying the results in more detail when the paper is published.

In the afternoon I gave my first talk of the week, but it followed right after Gurpreet Singh of Intel described the use of DSA rectification combined with EUV to print 21 nm and 18 nm pitch patterns using what is called self-aligned litho-etch-litho-etch (SALELE, pronounced “sah-lee-lee”).  He has been promoting this approach for a few years now, and this year including yield and electrical resistance data for the metal layer it was used on.  Compared to EUV-only patterning, the DSA approach produced extremely better yield and performance at the 18 nm pitch (and was easier to control at the 21 nm pitch).  The results are quite impressive.

My paper immediately followed and was an EPE analysis of data from that same Intel process (Gurpreet was a coauthor).  Using the EPE modeling approach that I introduced last year, measurements of the stochastics of the DSA line/space patterning and the alternative EUV-only patterning were combined with measurements of the via patterning that contacts with these metal lines to predict failure rate (in particular, the probability that a via would short to a neighboring line).  This enabled the modeling of the overlay process window (OPW), the range of overlay errors that can be tolerated while keeping the failure rate below some maximum allowed.  This approach translates the measurements of stochastics (such as LCDU or LEPE) into more tangible benefits such as the size of the OPW.  The results explained the yield behavior seen in Gurpreet’s prior paper, making our two papers a tandem endorsement for this DSA process.

I was coauthor on another Intel paper that afternoon as well, this one given by Pulkit Saksena.  Call me biased, but I thought Pulkit’s paper was great.  (Let me get the obvious pun out of the way:  I was biased, but Pulkit’s roughness measurements were not.)  He explained how Intel uses Fractilia’s MetroLER for material selection (main message, you must include etch in the evaluation, and PSDs (the power spectral density of the roughness data) are key to understanding the different between after litho and after etch roughness.  He then showed how the NILS difference between two scanner illumination sources did not predict the roughness difference that resulted (again, PSDs were useful in diving into the details).  Finally, he talked about EUV scanner matching.  Three scanners running the same process with the same mask had matched CDs (for three different pitches), but not matched LWR (the biggest difference was at the smallest pitch).  For the three scanners there was a 7% range in unbiased LWR for 32 nm pitch single-print patterns.  I think this is the first time anyone has reported such a difference between EUV tools, but I suspect others will be investigating this kind of matching soon.

In the metrology session at the end of the day there were several talks about using high-voltage CD-SEMs to measure two layers at once, allowing direct measurement of in-die EPE.  I think this approach is a great complement (but not a replacement) for the indirect EPE modeling that I talked about in my paper earlier in the day.  The last talk I saw was Jack Wong of IBM looking at the sources of NZO (the non-zero offset between optical scribe-line measurement of overlay after development compared to the in-die measurement of device overlay after etch).  His definition of NZO was a mean plus three-sigma value, and in my mind, it is the three-sigma (what I call NZO variability) that is the biggest worry.  His sources of variation analysis was quite nice.

As always on Tuesday night I experienced the hospitality of my friends at the resist companies (plus KLA) – thank you!

2 thoughts on “SPIE Advanced Lithography and Patterning Symposium 2024 – day 2”

  1. Thanks fot the amazing summary.
    Did Intel mentioned anything about in which year their 14A would be ready for production?

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