Tag Archives: Moore’s Law

SPIE Advanced Lithography and Patterning Symposium 2024 – day 2

The plenary session was split into two days this year, with two plenaries on Tuesday morning.  Ann Kelleher of Intel talked about her view of the new era of Moore’s Law: system technology co-optimization (STCO).  This is in addition to, not replacing, the prior eras of geometric scaling and design technology co-optimization (DTCO).  The new Moore’s Law metric is not the number of transistors on a chip, but the number of transistors in a package, with a goal of one trillion by 2030.  Some quotes from her presentation that stood out for me:

“DSA (directed self-assembly) is a key innovation that needs to be brought to high volume manufacturing.”

“The line between silicon and advanced packaging is blurring.”

Intel has been promoting their catch-up plan for close to two years now – five nodes in five years, culminating in the Intel 14A node, before starting back to a more relaxed two-year cadence.  But interestingly, the 14A node is expected to have a transistor density that is only 1.2X the 18A node.  In the past we might have called that a half-node, or even a shrink version of the existing node.  But maybe this is the new normal – smaller node-over-node improvements.

Chan Hwang of Samsung gave a plenary on lithography for memory production.  He spoke about many things that are front and center in my mind, especially contact hole edge placement error (EPE) and one of its largest components, local critical dimension uniformity (LCDU).  For EUV, the key to success is controlling LCDU at low dose.  Since the knobs for lowering stochastic LCDU are limited, their focus is on reducing global CDU to give more budget for LCDU.

Later in the morning there were several papers on a topic that has been bedeviling EUV lithography for some time:  image fading due to mask 3D effects.  For the case of dipole illumination (needed for the tightest pitches), the mask 3D effect causes a phase shift between the two diffraction orders, which results in an image shift.  Since the right pole shifts the vertical lines in one direction and the left pole shifts them in the oppositive direction, the result is an unshifted image with lower contrast and image log-slope.  The best long-term solution is to lower the mask 3D effects using new mask absorber materials, but that is still some years away.  In the meantime, Eelco van Setten of ASML described details of one proposal to add aberrations to compensate for this phase shift.  Of course, this makes many people nervous (we’ve been working on lowering aberrations for decades), especially since most masks include both tight-pitch lines and spaces plus other patterns that would be harmed by such aberrations.  Jieun Song of Samsung used a more traditional approach – source mask optimization (SMO), this time for staggered arrays of holes with the goal of reducing LCDU.  I have to admit, though, that this has a similar downside of being ideal only for the tight pitch holes and not for the other patterns on the mask.

Emily Gallagher ended the morning in the Optical and EUV Nanolithography conference with a talk about how mask roughness transfers to the wafer.  This topic has been around for many years (I wrote my first paper on it in 2009), but imec has taken a novel approach.  They programmed “random” roughness on the mask (not square waves of different amplitudes and periods that others have done in the past).  Jogs of various lengths and widths allowed control of both the mask LER and its correlation length.  Both the mask and the wafer printed with it were then measured.  I look forward to studying the results in more detail when the paper is published.

In the afternoon I gave my first talk of the week, but it followed right after Gurpreet Singh of Intel described the use of DSA rectification combined with EUV to print 21 nm and 18 nm pitch patterns using what is called self-aligned litho-etch-litho-etch (SALELE, pronounced “sah-lee-lee”).  He has been promoting this approach for a few years now, and this year including yield and electrical resistance data for the metal layer it was used on.  Compared to EUV-only patterning, the DSA approach produced extremely better yield and performance at the 18 nm pitch (and was easier to control at the 21 nm pitch).  The results are quite impressive.

My paper immediately followed and was an EPE analysis of data from that same Intel process (Gurpreet was a coauthor).  Using the EPE modeling approach that I introduced last year, measurements of the stochastics of the DSA line/space patterning and the alternative EUV-only patterning were combined with measurements of the via patterning that contacts with these metal lines to predict failure rate (in particular, the probability that a via would short to a neighboring line).  This enabled the modeling of the overlay process window (OPW), the range of overlay errors that can be tolerated while keeping the failure rate below some maximum allowed.  This approach translates the measurements of stochastics (such as LCDU or LEPE) into more tangible benefits such as the size of the OPW.  The results explained the yield behavior seen in Gurpreet’s prior paper, making our two papers a tandem endorsement for this DSA process.

I was coauthor on another Intel paper that afternoon as well, this one given by Pulkit Saksena.  Call me biased, but I thought Pulkit’s paper was great.  (Let me get the obvious pun out of the way:  I was biased, but Pulkit’s roughness measurements were not.)  He explained how Intel uses Fractilia’s MetroLER for material selection (main message, you must include etch in the evaluation, and PSDs (the power spectral density of the roughness data) are key to understanding the different between after litho and after etch roughness.  He then showed how the NILS difference between two scanner illumination sources did not predict the roughness difference that resulted (again, PSDs were useful in diving into the details).  Finally, he talked about EUV scanner matching.  Three scanners running the same process with the same mask had matched CDs (for three different pitches), but not matched LWR (the biggest difference was at the smallest pitch).  For the three scanners there was a 7% range in unbiased LWR for 32 nm pitch single-print patterns.  I think this is the first time anyone has reported such a difference between EUV tools, but I suspect others will be investigating this kind of matching soon.

In the metrology session at the end of the day there were several talks about using high-voltage CD-SEMs to measure two layers at once, allowing direct measurement of in-die EPE.  I think this approach is a great complement (but not a replacement) for the indirect EPE modeling that I talked about in my paper earlier in the day.  The last talk I saw was Jack Wong of IBM looking at the sources of NZO (the non-zero offset between optical scribe-line measurement of overlay after development compared to the in-die measurement of device overlay after etch).  His definition of NZO was a mean plus three-sigma value, and in my mind, it is the three-sigma (what I call NZO variability) that is the biggest worry.  His sources of variation analysis was quite nice.

As always on Tuesday night I experienced the hospitality of my friends at the resist companies (plus KLA) – thank you!

SPIE Advanced Lithography and Patterning Symposium 2024 – day 1

Monday began with awards, as always.  The new group of SPIE fellows from the lithography community had a very international flavor this year:  Soichi Inoue (Kioxia), Myungjun Lee (Samsung), Ted Liang (Intel), Mark van de Kerkhof (ASML), and Jan Van Schoot (ASML).  Congratulations!  The Nik Cobb Memorial Scholarship was presented to Nicholas Jenkins of the University of Colorado at Boulder.

I was extremely happy to see that Richard Sandstrom is this year’s winner of the Frits Zernike Award for Microlithography, our community’s highest honor.  Richard got his PhD from the University of California San Diego in 1979 and seven years later co-founded Cymer with his college friend Bob Akins.  Richard was chief scientist and their excimer lasers quickly became industry enablers for 248 and then 193 nm lithography.  I think it was only two years after the founding of Cymer when they shipped their first excimer light source.  The development of the EUV light source was also directed by Sandstrom, though it took a bit longer!  These light sources have always been critical to the success of Moore’s Law and lithography’s role in it, and Richard’s contribution for over 30 years was seminal.  Congratulations!

It was good to welcome Todd Younkin back to this conference.  He abandoned the field of lithography after ten years at Intel to become the CEO of SRC (Semiconductor Research Corporation), and his talk focused on SRC’s role in charting a sustainable future for semiconductors.

The industry giant Gordon E. Moore died last March at the age of 94.  His influence on the lithography community was profound (his insights that became Moore’s Law, the founding of Intel, even his 1995 plenary talk at this conference) and so the symposium decided to remember him with a very special Tribute Session.  Harvey Fineberg, President of the Gordon and Betty Moore Foundation, gave a video speech about his ongoing legacy of charitable contributions.  Craig Barrett, former Intel CEO, provided many moving stories about his times with Moore, and their joint love of fishing.  A main theme: while a very quiet man, when Gordon Moore spoke, people listened.  Paolo Gargini, former Director of Technology Strategy at Intel, provided a personalized history of Moore’s role in Moore’s Law (in classic Gargini style:  80+ slides in 20 minutes).  Dan Hutcheson of Tech Insights described Moore as a “gentle giant” that believed in the fundamentals.  Dan provided my favorite quote of the day: “Moore’s Law is about us and our ability to innovate.  It is not a law; it is an opportunity.”  Finally, Burn Lin and Martin van den Brink tied Moore’s Law to our community by giving each their own take on the history of lithography.  It was a great tribute.  (Aside: the announcement of Martin van den Brink’s imminent retirement from ASML provoked a standing ovation for his contributions to our community.)

The regular conference talks began in the afternoon, and I started with an invited talk by Andras Vladar (NIST) commemorating the 40-year anniversary of the first CD-SEM (introduced by Hitachi in 1984).  I agree with him when he said there are no low hanging fruits for improving SEM technology, but there are fruits.  The future of SEM technology in the semiconductor industry “is bright.”

The end of the talks on Monday is always a highlight for me, since it marks the beginning of the Fractilia Happy Hour – thanks to everyone who came!

SPIE Advanced Lithography Symposium 2016 – a prologue

2016 will prove to be a pivotal year in the history of semiconductor lithography.  How do I know this?  Because every year proves to be a pivotal year in the history of lithography.  Why should 2016 be any different?  Our industry moves too fast to allow a slack year.

I am frequently reminded of Sturtevant’s Law, not just because it is cute and funny (though it is), but because behind the humor lies a profound truth.  Sturtevant’s Law says that the end of optical lithography is 6 – 7 years away.  Always has been, always will be.  When I started in the field of lithography way back in 1983, Sturtevant’s Law was as yet unformulated but nonetheless in full swing.  X-ray or e-beam lithography was sure to take over by 1990 since it was obvious that optical lithography could not cross the 1 micron barrier.

This was but one of many, many failed predictions of the end of optical lithography.  But the fundamental truth behind Sturtevant’s Law is this:  we always know what we are doing for the next node (in 2 – 3 years), and are pretty sure about the node after that, but we have almost no visibility into what comes next.  We know all of the unsolved problems looming beyond the 6 year horizon, and can’t quite picture the solutions.  Sturtevant’s Law is a statement about our research and development timelines and how they relate to the pace of Moore’s Law.

But while Sturtevant’s Law has been in force for over 30 years, I’m afraid that it may be coming to an untimely end.  The reason is simple:  we no longer have good visibility out to two nodes (6 years).  We have a just barely reasonable impression about what the next node will bring, and are sure that the node after that is impossible.  The end of optical lithography is no longer 6 -7 years away, it is 2 – 3 years away, and even that time frame seems impossibly distant and opaque.

Our angst is about more than just lithography.  Of course, we lithographers know that the industry moves to the pace that we set.  Still, it is disconcerting to believe that a slowdown in lithography means the end of Moore’s Law.  Yet that is what is at stake.  In 2016, we must discover a path that keeps Moore’s Law moving forward, or watch Moore’s Law fall flat.

But a slowdown of Moore’s Law has already begun.  Intel’s 14-nm node was a year late, and Intel has admitted that its 10-nm node will also be late, on a 3-year node pace rather than the historic 2-year cycle.  TSMC has not admitted the slow-down, but is experiencing it anyway.  They created a “faux” node, a 16-nm product line that has the same dimensions and density as the previous 20-nm node.  Revealingly, when the 16-nm node came online last year, they did not report the revenues of that node separately as had been their normal practice, but rather began to lump the 16 and 20-nm node revenues together in one bucket.  “Follow the money” was good advice coming from Deep Throat, and is good advice in the semiconductor industry as well.

Moore’s Law is slowing down because lithography is not keeping up.  Multiple patterning is expensive and process control is a serious problem.  No other solutions are available.  Now, this where EUV is supposed to come in and save the day, right?

Alas, EUV is late.  ASML has made very good progress in the last two years, but that progress has been enough to keep EUV late, not enough to catch up with the industry need.  Anyone who has read these conference blogs before knows that I have been and continue to be an EUV skeptic.  But for the first time in over 20 years of development, I finally see a glimmer of hope for EUV.

Time is the enemy of all lithography development programs.  The demands of lithography move at an unrelenting pace, and even the slightest schedule slip in a lithography development program is the kiss of death.  EUV is late, an almost unmistakable sign of failure, and yet finally there is hope.  And here is the reason.

EUV was supposed to save Moore’s Law.  But instead, the slowdown of Moore’s Law may save EUV.

The 10-nm node will be two years late compared to the original schedule (naming games aside), as we are now on a three-year Moore’s Law cycle.  But since EUV is more than two years late, it still could not impact that node.  How late will the 7-nm node be?  Could it be late enough to use EUV?  That is a distinct possibility.

The big picture of lithography is bigger than the picture we will see at the SPIE Advanced Lithography Symposium in 2016, since the big picture involves the macroeconomics of the semiconductor industry itself.  But what we will see here this week is still big and very important.  How painful is multiple patterning really?  How close is directed self-assembly to being production worthy?  What is the status of nanoimprint manufacturing for Flash production?  Has there been any progress in taming the roughness beast?  And of course, what about EUV source power?

There are always many questions coming into the start of the SPIE lithography conference.  I am excited to start learning the answers.