Day four requires significant effort to stay mentally focused.  For me, I think it is less of a “brain is full” phenomenon and more lack of sleep and too much beer.  There is also my frustration with the SPIE conference app and the lack of a printed program.  Regardless of who is to blame, I am sad that my morning confusion led me to miss Hank Smith’s talk.  I heard it was great, filled with zone plates, Uranium-238, and a 4.5 nm wavelength.  This picture by John Petersen captures the moment, with Hank soon to be introduced by Bruce Smith.

I’m not sorry, however, that I attended Karey Holland’s talk on resists and the semiconductor roadmap (a slide deck that will make great reference material), or Yasin Ekinci reviewing capabilities and results from the Paul Scherrer Institute (PSI) and its EUV interference tool. 

The second half of the morning was the traditional “tool session”, though it remains strange (and maybe even a little sad) that all the talks were given by ASML and Zeiss.  What the session showed quite clearly is that our industry is driven by the equally important activities of invention and incremental progress.  And no companies excel at both like ASML and Zeiss.  Inventions, like EUV scanners or high-NA EUV scanners, do not initially result in something useful for the industry.  Instead, they provide a platform, a foundation, for the incremental advances which turn those inventions into useful, then essential, tools.  Sometimes those incremental advances seem exceedingly slow (as progress in EUV tooling did in 2010), but persistence and a steady pace has a way of paying off.  That was on full display during this session.  The ASML “low-NA” production systems continue to improve in overlay performance and source power, as Peter Klomp and Qiushi Zhu showed.  Source power increases are described as throughput improvements, but they could be equally described as resolution improvements since the entitlement resolution of a 0.33 NA EUV system can only be realized with enough dose to overcome stochastic limitations.  Progress in the High-NA EUV tools, described by Herman Heijmerikx, Hilbert van Loo, and Claus Zahlten in separate talks, shows that this new platform for innovation is here.  Now begins the incremental advancement that will make it work for the industry.

By the afternoon I was session hopping again.  First the Etch conference to hear a talk by my friends at Sandbox Semiconductor and then to give one myself.  Then back to optical and EUV to hear Luciana Meli of IBM say “Co-optimization of all patterning technologies is required for stochastics,” while showing IBM’s progress in that co-optimization for high-NA EUV.  Finally, it was back to my home conference of metrology for the Late News session, where among others I saw Hitachi talk about their new CD-SEM, the GT 2000.

It was a race to the finish (so it seemed), then the week was over.  But the residue of ALP remains, firstly with the papers that I still have to finish writing, but mostly with the ideas that I have to work through to see where they lead.  Another great year!

Wednesday was a day full of papers, culminating with the poster session.  Bright and early at 8:00 am Alain Moussa of imec reviewed progress towards in-line AFM.  While not diving into the specifics of individual AFM products, he showed results indicating that the main AFM weaknesses (probe stability and lifetime, especially for thin and narrow probes, and scan speed) have shown great improvement in recent years.  A particular difficulty is high aspect ratio holes and trenches.  He showed decent results for holes with an aspect ratio of 3 and trenches with an aspect ratio of 8, which is quite reasonable.  Later, an AFM manufacturer told me that even higher aspect ratio holes can be measured reliably.

The roadmap for implementing high-NA EUV lithography includes many difficult and time-consuming steps, most of which are outside of the control of the user.  But one step that every chipmaker would like to shorten as they prepare for those first high-NA wafers is OPC model calibration.  Good printing results for real device patterns require good OPC, which at the highest resolutions must be tuned to the specific aberrations and other non-idealities of the scanner.  A simple approach would wait until the high-NA EUV scanner was installed and accepted (with final system adjustments completed) before printing the wafers that begin the OPC calibration cycle.  Can (pronounced “John”) Guven of Intel described a novel solution that takes advantage of how good rigorous simulations have become.  Before the EUV scanner is shipped, aberrations are measured, then modified for expected improvements in final optics adjustments.  Those aberrations and other information are used in simulations to predict printing differences between early wafer results and what they expect final results to be, thus enabling better OPC calibration at an earlier stage in the scanner installation cycle.  Of course, there are lot details (and probably a few major concepts) that I am ignoring and/or getting wrong, but this seems like a good idea that works.

Wataru Yamane of Hitachi, along with coauthors at NIST, gave the talk that takes the prize (so far) for the most rigorously scientific and well-executed work at this conference.  With the goal of improving the accuracy of CD-SEM imaging simulations, they systematically explored various options for modeling low energy electrons as they travel and scatter through a sample, then compared simulations to very carefully measured SEM and transmission SEM data.  Moving the needle on SEM simulation accuracy is not easy; it is good to see valuable progress such as this.

Directed Self Assembly (DSA) was originally thought to be a technique to improve resolution through pitch division:  conventionally print a pattern at pitch P, then use that pattern to direct the self-assembly of block copolymers at pitch P/N, with N = 2, 3, 4, or even 5.  The promise of “resolution in a bottle” from DSA has never been fully realized for a variety of reasons.  But along the way another use for DSA become appreciated:  rectification of EUV-printed patterns by letting N = 1.  The idea is not to improve the resolution of the patterns, but rather to improve their quality, that is, their roughness.  DSA rectification has been shown to enable EUV dose reduction by a factor of 2 while simultaneously reducing stochastics effects compared to the full dose.  For low-NA EUV, with pitches as low as 24 nm, the best DSA material is PS-b-PMMA, a material that is well known, well tested, and ready for use in manufacturing (at least so claimed by people more knowledgeable than me).  To use DSA rectification below this pitch, however, requires both high-NA EUV patterning and a new class of DSA materials called high-Chi block copolymers. Victor Monreal of EMD showed good progress in the development of high-Chi materials, though more work is still needed. 

Brian Watson of Micron described experimental techniques for answering an important but difficult question:  where does line-edge roughness (LER) come from?  This breaking down of LER into components requires both good experiments and clever analysis.  The basic idea is to take one component of LER that can be individually manipulated and look for changes in LER with that parameter.  For Micron’s analysis of a 193i process, they began with speckle, randomness in exposure dose caused by unwanted coherent interactions from the ArF laser.  Speckle is proportional to one over the square root of the number of laser pulses, and that can be manipulated without affecting any other LER component.  The experiment showed the expected result:  LER is reduced as the number of pulses is increased (keeping dose constant).  But the LER change was quite small, so extremely good metrology (and a lot of it) was an enabler for this approach.  The next step was harder: separating the influence of the image from that of the resist by extrapolating LER versus 1/NILS (or its exposure latitude equivalent) to the case of a perfect image.  I’m going to have to study the paper when it comes out before rendering judgement on the details, but I commend Micron for taking on such an important and ambitious project.

One of the coolest ideas in stochastics is the Conservation of Roughness principle:  the LWR of an infinitely long line partitions into both roughness and local CD variations for a shorter line in specific way that is controlled by the correlation length of the roughness.  We tend to measure roughness for long lines, but the impact of stochastics on devices tends to occur on a short length scale – a device-relevant length that depends on the layer and the device.  It was great to see Gopal Kenath if IBM apply these concepts in a very practical way when comparing three photoresists.  It was also very interesting to see how different illuminators affected roughness by changing PSD(0), the low-frequency component of roughness, rather than the correlation length or roughness exponent.  I’m looking forward to his future work, where after-etch results will be analyzed in this same way.

I finished out the night (at least the technical portion of the night) by hanging out in front of my poster.  Thanks to SPIE for providing way-above-average quality beer, and to Bill Usry (one of my coauthors on the poster) for relieving me halfway through the session so I could enjoy that beer.

The second plenary session began with the announcement of the new SPIE fellows from our community: John Fourkas of the University of Maryland, Doug Guerrero of Brewer Science, Seiji Nagahara of ASML, and Eric Panning of SiClarity.  Congratulations!  There was also a tribute to Bob Dennard who died last year.  Dennard of IBM was the inventor of the single-transistor DRAM and the developer of “Dennard Scaling”, the CMOS scaling rules that formed the explanation for why Moore’s Law worked so well for so many years.  I loved this quote from him: “If you want to be successful, attitude is everything.”

The first plenary talk was by Christophe Fouquet, the new President and CEO of ASML.  Unlike the previous CEO, Christophe is a technical guy, coming up through the engineering ranks of the semiconductor industry at Applied Materials and KLA before going to ASML.  It was nice to have him speak to this community directly.  He showed an example of why Moore’s Law keeps going despite all of the difficulties:  we keep redefining Moore’s Law.  His plot of Number of Transistors per year (on a log scale) now shows the number of transistors per package rather than per chip.  He described the power problem also mentioned by Shien-Yang Wu, that the power used to train AI models is growing 10X per year, a completely unsustainable trend that must end in the next one or two years.  One possible solution is Processing in Memory, putting CPU-like capabilities on the DRAM chip (which has the added advantage of being 16X faster).  This idea has been around for a long time but resisted since it makes the DRAM part of the chip cost about as much per unit area of silicon as the CPU.  This crazy idea (increasing the cost of your memory by an order of magnitude or more) doesn’t seem as crazy in the era of $1000+ Nvidia chips.

Nelson Felix of IBM stepped in as a last-minute substitute speaker for Heike Riel, who had travel problems.  He did an impressive job.  The first half of the talk was an overview of traditional computer performance scaling and I noticed one graph crowded among others that showed the cost per transistor reached a minimum at the 28 nm node.  I’ve seen this type of plot before, but not from a chipmaker.  This section ended with an incredible quote:  “Process control is the new scaling.”  The second half of the talk was devoted to IBM’s progress in Quantum Computing and it was impressive.  With their superconducting (Josephson Junction) qubit approach they have integrated more that 1000 qubits onto a chip.  To be clear, these are physical qubits, not logical qubits.  The number of logic qubits is the “N” that goes into the 2^N equation that everyone shows to explain the incredible potential of quantum computing.  But due to a very short decoherence time many redundant qubits are required for error correction, and the ratio of physical qubits to logical qubits is very high (up to 1000).  Pushing this ratio down is extremely important to the success of quantum computing and the reason that quantum computer development is not just a scaling game of increasing physical qubits.  IBM’s claim is that qubit stability is also improving and the number of logical qubits available (a number never mentioned) has reached the point where quantum computers can now rival classical computers for some real-world problems.  This “quantum supremacy” point has been claimed many times by many companies in press releases over the last few years, and I never believe them.  It looks like IBM may be close.

Updates on the readiness of negative tone metal oxide resists for EUV exposure showed nice progress.  Lam’s dry resist continues to improve its stochastics, as seen in talks by Zhengtio Chen of Lam and Indira Seshadri of IBM.  Both supplemented traditional LER/LWR measurements with electrical defectivity using meander and fork patterns to detect line/space bridges and breaks with defectivities as low as one per meter line length.  In the patterning materials conference Samsung used a metal oxide resist with a brightfield mask to print contact holes with reduced dose and low local CD uniformity (LCDU, though Samsung calls it IPU, CD “in-point uniformity”).

An aside:  it seems that SPIE has given up on its “No Photography” policy during talks and instead relaxed it to no video recordings.  I suppose this is reasonable since the no photography rule was uniformly ignored.  As I jumped from the optical and EUV conference to the materials conference and sat in the back of the room, the implications of this change were evident.  At every slide change by the speaker, one hundred cameras rose up in unison around the room to take pictures of the new slide, as if choreographed.  It is now allowed, but it is still distracting.

The afternoon brought me back home to the metrology conference.  Gian Lorusso showed very interesting results on the use of a high-voltage (15 kV) CD-SEM to improve the resolution for high-NA EUV printed patterns.  (Full discloser – I am a coauthor on that paper.)  The typical 500 V imaging is running out of steam, since the interaction volume of the electrons within the resist is large enough that when the beam strikes one edge of a < 10 nm wide feature, some electrons escape out of the other edge.  This correlates the roughness of the two edges, making LWR measurement impossible.  A higher voltage not only increases the resolution of the SEM, it reduces the left-right edge correlation of small features and makes LWR measurement possible again.  The worry, of course, is sample damage (and especially resist shrinkage).  After all, we have been regularly reducing voltage to reduce shrinkage.  Lorusso’s thesis is that lower voltage is better up to a few kV, but that even higher voltages might in fact reduce sample damage (at least in the top layer) by having electrons deposit more of their energy deeper into the substrate.  His preliminary shrinkage data bore this theory out, and I suspect we will here more about high-voltage measurement of small patterns in the future.

I gave a talk with imec on the stochastic failure of vias to make electrical contact with metal line-ends.  Using a modeling approach that Mike Adel and I developed over the last few years (and recently published in JM3), measurement of via stochastic variations coupled with line-end tip-to-tip variations were used to predict variations in overlap area between the hole and the line-end.  Given a minimum required area of overlap, these measured stochastic variations can be translated to failure rates as a function of overlay error between the two layers.  What is the minimum area of overlap required for a good electric connection?  That number was determined by comparing the model results to voltage contrast measurements.  The fit of the model to the data was excellent, if I do say so myself.

Alas, my afternoon was taken up with customer meetings.  I love meeting with my customers, but don’t like missing so many good talks.

My day came to a very satisfying end at the KLA party celebrating 40 years of PROLITH.  As I mentioned earlier, I gave my first-ever conference talk at this conference in 1985 and introduced PROLITH to the world.  At the end of that talk I mentioned that I would send the software (free) to anyone who gave me their business card.  I got 80 cards.  Using the language that I now understand, I would call that an indicator of market demand.  Five years later I started FINLE Technologies to commercialize PROLITH.  After adding some great people to the team, like Ed Charrier and Mark Smith, we sold FINLE to KLA in 2000.  I left KLA in 2005, and I am proud to say that I don’t think they even missed me.  Today PROLITH is doing amazingly well, providing the most rigorous full-chip simulations available – a truly amazing accomplishment.  Looking at that timeline, you can see that PROLITH has been outside of my tutelage for just as long as it was under it.  Congratulations to the PROLITH team, and good luck for the next 40 years!

The opening remarks for the symposium revealed what was already obvious – the six conferences that make up ALP are doing very well.  There were 536 abstracts submitted and registration stood at 2200 attendees, both excellent numbers indicating a thriving meeting.  I was very excited to see Hank Smith of MIT accept his Frits Zernike Award for Microlithography.  Hank may be best known for his significant work on X-ray lithography in the 1970s and 80s, but his contributions to phase-shifting masks and numerous nanolithography approaches have also been important.  And as his award citation pointed out, the legacy of his students greatly extends the reach of his influence.  Congratulations, Hank!

This year the four plenary talks are spread over two days, with the first two on Monday.  Shien-Yang Wu of TSMC gave an obligatory nod to Artificial Intelligence in his talk about technological progress at the world’s leading semiconductor company.  I don’t blame him for his excitement about AI, since it is expected to add up to $200B to annual semiconductor revenue by 2030, with TSMC destined to take the lion’s share.  His talk touched on several important themes:  the growing role of packaging in keeping the evolving Moore’s Law alive; the challenge of power consumption as AI tries to consume all the data in the world; the trend toward verticality in logic transistors; the many innovations beside lithography scaling that contribute to transistor density improvements.

Subramanian Iyer of UCLA went deeper into one of those topics in his plenary on strategic directions for packaging.  I liked his description of the dual purpose of packaging as “protect and serve”:  protect the chip mechanically and from the environment while serving up electrical connections to other chips.  The key trends in packaging are all about the optimization between increasing the functionality of a monolithic chip (with the higher costs that come from a larger die) and the performance loss that comes from the limitations in I/O when that functionality is spread between chips.  This optimization can be improved by reducing the limitations of the “serve”, getting the signals on and off the chips.  This can be done by making the packaging interconnections (such as the bump pitch) closer in size to the pitch of the top wiring level of the chip (that is, closer to 1 micron from today’s 10 microns) and by reducing the length of the interconnects (bringing the chips closer to each other) so that those interconnects become wires rather than transmission lines.

The opening of the metrology conference began with a touching tribute to Ben Bunday, who died suddenly last August at the age of 55.  Ben was a constant presence at this conference for 25 years, with 104 SPIE papers (two of which won the Diana Nyyssonen Best Paper Award) and 15 years as a member of the metrology conference program committee.  I count Ben as an important colleague (we wrote many papers together and were planning one for 2025) and remember him as a friend.  The standing ovation for him at the end of the tribute was fitting.

Master Younghoon Sohn of Samsung gave a keynote talk in the metrology conference on the evolution of eBeam MI (metrology and inspection) technology.  He described the purposes of MI as monitoring process defects and quantifying the process window.  The talk was structed as an increase in “dimensionality” of SEM metrology, from a 2D top-down SEM image, to a 4D description of a material property in 3D space, to the “next” level of monitoring that 4D description over time.  His mention of my favorite subject was this: “Roughness? Defining the accuracy is quite difficult.”  Very true.

I snuck over to the patterning materials conference to watch Mihir Gupta give a review of imec’s approach to resist evaluation.  Imec has pioneered the addition of the “failure free latitude” to the conventional RLS trade-off (resolution, line-edge roughness, and sensitivity) and Mihir provided some valuable details of their method.

Back at the metrology conference in the afternoon, Applied Materials gave a pair of presentations exhibiting the triumph of marketing over science.  One talked of “True Metrology” and the measurement of the “True CD”.  Really?  Their use of these terms would make any true metrologist cringe.  The “True Value” of a measurand is inherently unknowable, requiring instead a comparison to a reference and an estimated bounding of the errors in the measurement.  This is Metrology 101, and nothing like this was described or even hinted at.  What the paper was about was the use of 150 V in the SEM to reduce resist shrinkage (compared to 500 V).  But to describe a measurement with lower shrinkage as the “True CD” is a distortion of not only what was done, but what is possible.

The other paper by Applied in that session was even worse:  Anna Levant’s talk “Beyond 3 Sigma: roughness metrology evolution at the last 20 years (in memory of Ben Bunday)”.  Purporting to be a review paper of roughness metrology this talk was instead an attempt to rewrite history and claim leadership (or even significant contributions) in roughness metrology by Applied Materials.  Besides “True CD” they have added another nonsensical term to the lexicon: the “noiseless PSD”.  This would just be another fluff paper, not worthy of ire, if it were not for the transparent and grotesque attempt to gain credibility for themselves through the memory of Ben Bunday.  The authors should be ashamed.

So as not to end this post on a sour note, I’ll mention the last presenter I saw giving the last paper of the optical and EUV conference, Tim Brunner.  Tim told me he was retiring next month, so this is likely his last SPIE presentation after 43 years of contributions.  (His first paper, from 1982, was in Optical Microlithography I: Technology for the Mid-1980s.)  Like many, I have been a Tim Brunner fan since I first heard him speak.  He is a paragon of sound reasoning, clear exposition, and good science.  He is also often quite funny, invariably inciteful, and frequently timely in his contributions, which are almost always important.  Tim, you are appreciated, and you will be missed.

The year 2025 has a nice, round ring to it.  I like round numbers, and it is especially true for me this year as I attend another SPIE conference on lithography.  That is because the first paper I ever presented at a conference was exactly 40 years ago, at the 1985 SPIE Microlithography Conferences held at the Mariott Hotel in Santa Clara, California.  That year the conferences were Electron-Beam, X-Ray, and Ion-Beam Techniques for Submicrometer Lithographies IV (27 papers), Optical Microlithography IV (33 papers), and Advances in Resist Technology and Processing II (44 papers), held 11-14 March, 1985.  That was the tenth SPIE Microlithography conference, the first one being in 1976.  My paper was called “PROLITH: A Comprehensive Optical Lithography Model”, and for anyone interested in such ancient history, the paper can be found here.  I remember very clearly that I remember nothing about giving that paper.  I was so nervous (but also had practiced so often) that giving the paper almost didn’t register in my consciousness.  But give it I did, and my career took off. 

It has been a fun 40 years! As I wander around the San Jose area on Sunday afternoon, I am already running into friends that I see only once a year, at this event, and others that I see all the time.  I’m reminded of how important this community has been to me, and not just from a business or professional perspective.  I don’t buy into the phrase “It’s only business.”  It’s never only business – everything is personal.  And that’s because, when I get to the bottom of what I do and why I do it, it’s always about people.  People I am very close to, people I see only once a year, and people I have never met.  They are all important, and they give me the sense that what I do matters.  That’s why I love being a part of this community, and why I keep coming back every year for 40 years.  What we do matters, and that matters to me.

And so conference number 41 begins for me.  Some things will be just like years past – a plenary session, new SPIE fellows, too many marketing talks and graphs without numbers on the axes, trying to stay awake through some talks and being so excited by others that I can’t wait to talk about them and think about them.  And some things will be unique – the new young person I meet that gives me hope for the future, the inspiring idea that I take back home and try to make use of, and the inevitable, incremental, interesting new progress that makes life and this career of mine interesting.  Let the conference begin!

The final day!  In the morning I watched the ASML updates on their EUV and DUV systems, working backwards from high-NA EUV.  Two high-NA systems are being put together almost simultaneously, one at the High-NA demonstration lab in Veldhoven, and one at Intel in Portland.  These tools should start running wafers at resolution “in a few weeks or months”, according to Jara Garcia-Santaclara.  Since design work began in 2014, a 10-year idea-to-print cycle is pretty good for a tool of this complexity.  On the low-NA EUV front, the new NXE:3800 has started shipping (though none are yet running at a customer site), with a 25% increase in source power and other changes to increase throughput and performance.

Anyone who has been paying attention knows that financial analysts have been coming regularly to this symposium for at least 20 years.  The consequences are never good.  Companies that care about their stock price (and that would be all companies that have a stock price) often require their authors to provide messages that they want to give to Wall Street, regardless of how it plays to the lithography community.  A perfect example was Peter Klomp, who gave a good talk on ASML’s low-NA EUV tools.  But it was padded with 6 or 8 slides at the front that were completely unnecessary for the lithography community and sounded like the kind of thing a CEO would say at the start of an investors’ day event.  Data is growing!  AI is coming!  People need more chips!  Ah well.

Yoji Watanabe of Nikon talked about their development of maskless DUV projection systems (both 248 and 193nm) using a digital mirror spatial light modulator in place of the mask.  They have a proof-of-concept system running, and some of its parameters were revealed.  It has a 193 nm wavelength with NA = 0.675.  The reduction ratio is “greater than 100” resulting in an exposure field less than 1 mm wide.  The pixel size at the wafer is 40 nm, and the current throughput is 0.5 wafers per hour.  Obviously all of these things will evolve (smaller pixel size, larger field size, higher throughput) as development proceeds, but the initially images looked pretty good.  There are definitely some devices where mask costs exceed most all other costs, so I can see the benefits of such a maskless system.

Chris Anderson of xLight shed some light on that start-up’s audacious plans for building Free Electron Laser (FEL) light sources for EUV manufacturing.  While everything they have is still only on paper (they are shooting for first light in 2027), he described a centralized FEL (a pair of them actually) that could feed up to 20 EUV scanners with 2kW of power (4X greater than the brightest sources currently available from ASML).  The cost of one of these sources would be about $500M (give or take a few $100M), so that is a pretty big bet, especially since ASML will get to decide if xLight even has a chance to compete.

After zipping over to the Directed Self-Assembly (DSA) session in the Novel Patterning conference, I learned from Lander Verstraete of imec that contact hole rectification with DSA is great in about all respects except one – local pattern placement error (LPPE).  While local CD Uniformity (LCDU) significantly improves after applying DSA (enabling low-dose EUV printing of the original holes), the LPPE gets worse.  Further optimization is required – I doubt it is a fundamental problem.  Tomoshiro Iwaki of Micron spoke about using DSA with 9X multiplication (3X pitch division in both X and Y) when printing staggered arrays of holes.  Iwaki-san presented a year’s worth of 1b DRAM yield data, showing an improvement up to the current 88.5% yield.  Still, the process is not in high-volume manufacturing for reasons that Iwaki-san was a bit cagey about, but I think related to the pattern placement error of the holes.

Rober Browning of Intel gave a short but sweet talk on using the Applied Materials Sculpta tool to shrink tip-to-tip spacing for the case of trenches (common to damascene metal layers).  The tool uses physical etching at an angle to preferentially increase etch bias in only one direction, and Intel used it to grow the length of a space without growing its width.  In Intel’s case they were able to replace an EUV double exposure process with a single exposure + Sculpta.  Very interesting, and it sounded like Intel has proven out its potential.

I left the conference to go home a few hours early, and so missed some good papers (including one I was a coauthor on with Ben Bunday).  As always, it was a fun but exhausting week.  The mood was upbeat, as the industry recovers from its 2023 doldrums.  2024 is off to a good start!

Wednesday was the peak of busy for me, attending many papers (and giving one).  It was also a very typical day in that almost all of the papers I saw were exactly what I expected:  incremental advances.  Nothing jaw dropping, just the small advances that have fueled this industry’s progress for the 40 years I have been involved. 

Jodi Grzeskowiak of TEL did a great job explaining their new “anti-spacer” process, using acid diffusion into a resist pattern to form a skin that turns into a negative tone version of a spacer pattern.  She described it as a “track-based pitch split.”  I was especially happy that the process didn’t have a cute acronym with a trademark symbol and no description of how it worked.

Indira Seshadri of IBM showed off what IBM is good at, optimizing all aspect of a process (in this case the Lam dry resist) to get high yield at tight pitches.  Hyeon Bo Shim of Samsung provided a simple geometric model for how electrons escape out of a contact hole (for the case of vertical sidewalls only), showing that the aspect ratio controls the visibility of the hole bottom.  Since I am a coauthor (with Ben Bunday) on a paper on a similar topic on Thursday, I was especially interested.  I’ve already checked out this Samsung geometric model against our SEM simulations and it works surprisingly well.

Boris Habets (KLA) collected overlay data on the “micron scale”.  He was able to measure overlay directly on the device, but did so in a memory cell so that he could achieve extremely high sampling over length scales we don’t normally interrogate.  Over a distance of a few microns overlay variations are not due to scanner effects, but rather shorter-range proximity effects.  In this case, each memory array tile (a few microns square) had a regular signature, possibly due to film stress relaxation.  The magnitude was a few tenths of a nanometer, but if stable and consistent would be correctable on the mask.

I attempted to attend the panel discussion on the future of EUV lithography, but was unsuccessful.  The event was standing room only, and I was unwilling the elbow my way through the crowd standing three deep at the door.  I hope it was useful.  I did make it to the poster session, however, and actually walked the whole circuit.  There were some nice posters and a fun crowd.