SPIE Advanced Lithography and Patterning Symposium 2023 – day 4

I began the last day of the conference at the EUV talks.  Jo Finders of ASML described how non-idealities of the scanner can effect single-layer edge placement errors (a combination of CD errors, both global and local, and local pattern placement errors).  This was the first time I had seen a numerical breakdown of mechanisms of “NILS loss”, the reduction of the Normalized Image Log-Slope from its theoretical value caused by mask topography, aberrations, flare, focus variation across the slit, etc.  The NILS loss totaled to 15%, and Jo described various approaches to get some of that back.

Suk-Koo Hong of Samsung provided “speculations” on why pushing k1 below 0.4 in EUV is problematic (specifically, for printing contact holes).  The reason is stochastics, and there seems to be a scaling with pitch and CD that is worse than the famous z-factor predicts:  z-factor = feature size^3 * LCDU^2 * Dose-to-size.  Plotting LCDU (local CD uniformity) versus dose produces higher than expected LCDU at the lowest doses and seems to be following a different iso-z-factor limit.  The specifics of CD and pitch and anything else that made up the data points in his graphs, however, were not revealed.  Still, it was an interesting way to look at the problem, one still without a solution.

As an aside, Samsung gave many papers this week, and some of those papers were some of the best in the conference.  Case in point: Hyungju Ryu presented work by Sangjim Kim (who couldn’t make it here) on process control for EUV metal oxide resists (MOR, read Inpria).  The two MOR challenges are CD variation due to sensitivity to humidity, and poor etch resistance.  Apparently, these problems are well known to the users of Inpria resists, but they weren’t being discussed publicly until now.  For example, CD was shown to vary by 2 – 8% depending on the post-coating delay.  Samsung showed, however, that careful optimization of every resist processing step reduced the CD variation to 35% of its original value.  Etch resistance of the MOR was not as good as expected since partially exposed resist does not have a well-connected network of core-to-core bonds necessary for best etch resistance.  Samsung’s solution was a UV flood exposure.  They said that more work was required to make the MOR ready for high volume manufacturing, but these were good steps in that direction.

On a completely different topic, Etienne Poortere of ASML showed how a carefully designed test mask coupled with voltage contrast metrology could be used to establish design rules for via connections to metal 1 in a dual damascene process of 28 nm pitch.  The technique made evaluation of a matrix of tip-to-tip spacings and M1 via overlap rules quite easy.

Back in the SEM world, Ofer Adan gave a good marketing talk on Applied Materials’ new cold field emission (CFE) electron source for their inspection SEMs (and maybe for the CD SEM?  It wasn’t clear.).  I’m convinced this new CFE source is better, but I don’t know why.

As is usually the case, by Thursday afternoon my brain had reached its absorption limit.  I continued going to talks, but my notes became brief as my attention strayed.  Summing up, this week lived up to my expectations – it was the Advanced Lithography and Patterning conference back to its full glory.  There were many solid talks – nothing earth shattering (but there rarely is), just good incremental progress towards the harder to reach goal of keeping Moore’s Law alive.  It’s a shame that the memory sector downturn kept many Micron and SK Hynix lithographers away, and that Intel’s troubles kept their attendance to a minimum.  It was gratifying to see so many good papers from Samsung, and decent attendance from TSMC.  I go away looking forward to next year.

One thought on “SPIE Advanced Lithography and Patterning Symposium 2023 – day 4

  1. Hi. I just discovered your Mom’s watercolors. I bought a card. “IBIS WALK” at the Penn Center but the only had one. Do you have any for sale?

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