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SPIE Advanced Lithography and Patterning Symposium 2024 – day 4

The final day!  In the morning I watched the ASML updates on their EUV and DUV systems, working backwards from high-NA EUV.  Two high-NA systems are being put together almost simultaneously, one at the High-NA demonstration lab in Veldhoven, and one at Intel in Portland.  These tools should start running wafers at resolution “in a few weeks or months”, according to Jara Garcia-Santaclara.  Since design work began in 2014, a 10-year idea-to-print cycle is pretty good for a tool of this complexity.  On the low-NA EUV front, the new NXE:3800 has started shipping (though none are yet running at a customer site), with a 25% increase in source power and other changes to increase throughput and performance.

Anyone who has been paying attention knows that financial analysts have been coming regularly to this symposium for at least 20 years.  The consequences are never good.  Companies that care about their stock price (and that would be all companies that have a stock price) often require their authors to provide messages that they want to give to Wall Street, regardless of how it plays to the lithography community.  A perfect example was Peter Klomp, who gave a good talk on ASML’s low-NA EUV tools.  But it was padded with 6 or 8 slides at the front that were completely unnecessary for the lithography community and sounded like the kind of thing a CEO would say at the start of an investors’ day event.  Data is growing!  AI is coming!  People need more chips!  Ah well.

Yoji Watanabe of Nikon talked about their development of maskless DUV projection systems (both 248 and 193nm) using a digital mirror spatial light modulator in place of the mask.  They have a proof-of-concept system running, and some of its parameters were revealed.  It has a 193 nm wavelength with NA = 0.675.  The reduction ratio is “greater than 100” resulting in an exposure field less than 1 mm wide.  The pixel size at the wafer is 40 nm, and the current throughput is 0.5 wafers per hour.  Obviously all of these things will evolve (smaller pixel size, larger field size, higher throughput) as development proceeds, but the initially images looked pretty good.  There are definitely some devices where mask costs exceed most all other costs, so I can see the benefits of such a maskless system.

Chris Anderson of xLight shed some light on that start-up’s audacious plans for building Free Electron Laser (FEL) light sources for EUV manufacturing.  While everything they have is still only on paper (they are shooting for first light in 2027), he described a centralized FEL (a pair of them actually) that could feed up to 20 EUV scanners with 2kW of power (4X greater than the brightest sources currently available from ASML).  The cost of one of these sources would be about $500M (give or take a few $100M), so that is a pretty big bet, especially since ASML will get to decide if xLight even has a chance to compete.

After zipping over to the Directed Self-Assembly (DSA) session in the Novel Patterning conference, I learned from Lander Verstraete of imec that contact hole rectification with DSA is great in about all respects except one – local pattern placement error (LPPE).  While local CD Uniformity (LCDU) significantly improves after applying DSA (enabling low-dose EUV printing of the original holes), the LPPE gets worse.  Further optimization is required – I doubt it is a fundamental problem.  Tomoshiro Iwaki of Micron spoke about using DSA with 9X multiplication (3X pitch division in both X and Y) when printing staggered arrays of holes.  Iwaki-san presented a year’s worth of 1b DRAM yield data, showing an improvement up to the current 88.5% yield.  Still, the process is not in high-volume manufacturing for reasons that Iwaki-san was a bit cagey about, but I think related to the pattern placement error of the holes.

Rober Browning of Intel gave a short but sweet talk on using the Applied Materials Sculpta tool to shrink tip-to-tip spacing for the case of trenches (common to damascene metal layers).  The tool uses physical etching at an angle to preferentially increase etch bias in only one direction, and Intel used it to grow the length of a space without growing its width.  In Intel’s case they were able to replace an EUV double exposure process with a single exposure + Sculpta.  Very interesting, and it sounded like Intel has proven out its potential.

I left the conference to go home a few hours early, and so missed some good papers (including one I was a coauthor on with Ben Bunday).  As always, it was a fun but exhausting week.  The mood was upbeat, as the industry recovers from its 2023 doldrums.  2024 is off to a good start!

SPIE Advanced Lithography and Patterning Symposium 2024 – day 3

Wednesday was the peak of busy for me, attending many papers (and giving one).  It was also a very typical day in that almost all of the papers I saw were exactly what I expected:  incremental advances.  Nothing jaw dropping, just the small advances that have fueled this industry’s progress for the 40 years I have been involved. 

Jodi Grzeskowiak of TEL did a great job explaining their new “anti-spacer” process, using acid diffusion into a resist pattern to form a skin that turns into a negative tone version of a spacer pattern.  She described it as a “track-based pitch split.”  I was especially happy that the process didn’t have a cute acronym with a trademark symbol and no description of how it worked.

Indira Seshadri of IBM showed off what IBM is good at, optimizing all aspect of a process (in this case the Lam dry resist) to get high yield at tight pitches.  Hyeon Bo Shim of Samsung provided a simple geometric model for how electrons escape out of a contact hole (for the case of vertical sidewalls only), showing that the aspect ratio controls the visibility of the hole bottom.  Since I am a coauthor (with Ben Bunday) on a paper on a similar topic on Thursday, I was especially interested.  I’ve already checked out this Samsung geometric model against our SEM simulations and it works surprisingly well.

Boris Habets (KLA) collected overlay data on the “micron scale”.  He was able to measure overlay directly on the device, but did so in a memory cell so that he could achieve extremely high sampling over length scales we don’t normally interrogate.  Over a distance of a few microns overlay variations are not due to scanner effects, but rather shorter-range proximity effects.  In this case, each memory array tile (a few microns square) had a regular signature, possibly due to film stress relaxation.  The magnitude was a few tenths of a nanometer, but if stable and consistent would be correctable on the mask.

I attempted to attend the panel discussion on the future of EUV lithography, but was unsuccessful.  The event was standing room only, and I was unwilling the elbow my way through the crowd standing three deep at the door.  I hope it was useful.  I did make it to the poster session, however, and actually walked the whole circuit.  There were some nice posters and a fun crowd.

SPIE Advanced Lithography and Patterning Symposium 2024 – day 2

The plenary session was split into two days this year, with two plenaries on Tuesday morning.  Ann Kelleher of Intel talked about her view of the new era of Moore’s Law: system technology co-optimization (STCO).  This is in addition to, not replacing, the prior eras of geometric scaling and design technology co-optimization (DTCO).  The new Moore’s Law metric is not the number of transistors on a chip, but the number of transistors in a package, with a goal of one trillion by 2030.  Some quotes from her presentation that stood out for me:

“DSA (directed self-assembly) is a key innovation that needs to be brought to high volume manufacturing.”

“The line between silicon and advanced packaging is blurring.”

Intel has been promoting their catch-up plan for close to two years now – five nodes in five years, culminating in the Intel 14A node, before starting back to a more relaxed two-year cadence.  But interestingly, the 14A node is expected to have a transistor density that is only 1.2X the 18A node.  In the past we might have called that a half-node, or even a shrink version of the existing node.  But maybe this is the new normal – smaller node-over-node improvements.

Chan Hwang of Samsung gave a plenary on lithography for memory production.  He spoke about many things that are front and center in my mind, especially contact hole edge placement error (EPE) and one of its largest components, local critical dimension uniformity (LCDU).  For EUV, the key to success is controlling LCDU at low dose.  Since the knobs for lowering stochastic LCDU are limited, their focus is on reducing global CDU to give more budget for LCDU.

Later in the morning there were several papers on a topic that has been bedeviling EUV lithography for some time:  image fading due to mask 3D effects.  For the case of dipole illumination (needed for the tightest pitches), the mask 3D effect causes a phase shift between the two diffraction orders, which results in an image shift.  Since the right pole shifts the vertical lines in one direction and the left pole shifts them in the oppositive direction, the result is an unshifted image with lower contrast and image log-slope.  The best long-term solution is to lower the mask 3D effects using new mask absorber materials, but that is still some years away.  In the meantime, Eelco van Setten of ASML described details of one proposal to add aberrations to compensate for this phase shift.  Of course, this makes many people nervous (we’ve been working on lowering aberrations for decades), especially since most masks include both tight-pitch lines and spaces plus other patterns that would be harmed by such aberrations.  Jieun Song of Samsung used a more traditional approach – source mask optimization (SMO), this time for staggered arrays of holes with the goal of reducing LCDU.  I have to admit, though, that this has a similar downside of being ideal only for the tight pitch holes and not for the other patterns on the mask.

Emily Gallagher ended the morning in the Optical and EUV Nanolithography conference with a talk about how mask roughness transfers to the wafer.  This topic has been around for many years (I wrote my first paper on it in 2009), but imec has taken a novel approach.  They programmed “random” roughness on the mask (not square waves of different amplitudes and periods that others have done in the past).  Jogs of various lengths and widths allowed control of both the mask LER and its correlation length.  Both the mask and the wafer printed with it were then measured.  I look forward to studying the results in more detail when the paper is published.

In the afternoon I gave my first talk of the week, but it followed right after Gurpreet Singh of Intel described the use of DSA rectification combined with EUV to print 21 nm and 18 nm pitch patterns using what is called self-aligned litho-etch-litho-etch (SALELE, pronounced “sah-lee-lee”).  He has been promoting this approach for a few years now, and this year including yield and electrical resistance data for the metal layer it was used on.  Compared to EUV-only patterning, the DSA approach produced extremely better yield and performance at the 18 nm pitch (and was easier to control at the 21 nm pitch).  The results are quite impressive.

My paper immediately followed and was an EPE analysis of data from that same Intel process (Gurpreet was a coauthor).  Using the EPE modeling approach that I introduced last year, measurements of the stochastics of the DSA line/space patterning and the alternative EUV-only patterning were combined with measurements of the via patterning that contacts with these metal lines to predict failure rate (in particular, the probability that a via would short to a neighboring line).  This enabled the modeling of the overlay process window (OPW), the range of overlay errors that can be tolerated while keeping the failure rate below some maximum allowed.  This approach translates the measurements of stochastics (such as LCDU or LEPE) into more tangible benefits such as the size of the OPW.  The results explained the yield behavior seen in Gurpreet’s prior paper, making our two papers a tandem endorsement for this DSA process.

I was coauthor on another Intel paper that afternoon as well, this one given by Pulkit Saksena.  Call me biased, but I thought Pulkit’s paper was great.  (Let me get the obvious pun out of the way:  I was biased, but Pulkit’s roughness measurements were not.)  He explained how Intel uses Fractilia’s MetroLER for material selection (main message, you must include etch in the evaluation, and PSDs (the power spectral density of the roughness data) are key to understanding the different between after litho and after etch roughness.  He then showed how the NILS difference between two scanner illumination sources did not predict the roughness difference that resulted (again, PSDs were useful in diving into the details).  Finally, he talked about EUV scanner matching.  Three scanners running the same process with the same mask had matched CDs (for three different pitches), but not matched LWR (the biggest difference was at the smallest pitch).  For the three scanners there was a 7% range in unbiased LWR for 32 nm pitch single-print patterns.  I think this is the first time anyone has reported such a difference between EUV tools, but I suspect others will be investigating this kind of matching soon.

In the metrology session at the end of the day there were several talks about using high-voltage CD-SEMs to measure two layers at once, allowing direct measurement of in-die EPE.  I think this approach is a great complement (but not a replacement) for the indirect EPE modeling that I talked about in my paper earlier in the day.  The last talk I saw was Jack Wong of IBM looking at the sources of NZO (the non-zero offset between optical scribe-line measurement of overlay after development compared to the in-die measurement of device overlay after etch).  His definition of NZO was a mean plus three-sigma value, and in my mind, it is the three-sigma (what I call NZO variability) that is the biggest worry.  His sources of variation analysis was quite nice.

As always on Tuesday night I experienced the hospitality of my friends at the resist companies (plus KLA) – thank you!

SPIE Advanced Lithography and Patterning Symposium 2024 – day 1

Monday began with awards, as always.  The new group of SPIE fellows from the lithography community had a very international flavor this year:  Soichi Inoue (Kioxia), Myungjun Lee (Samsung), Ted Liang (Intel), Mark van de Kerkhof (ASML), and Jan Van Schoot (ASML).  Congratulations!  The Nik Cobb Memorial Scholarship was presented to Nicholas Jenkins of the University of Colorado at Boulder.

I was extremely happy to see that Richard Sandstrom is this year’s winner of the Frits Zernike Award for Microlithography, our community’s highest honor.  Richard got his PhD from the University of California San Diego in 1979 and seven years later co-founded Cymer with his college friend Bob Akins.  Richard was chief scientist and their excimer lasers quickly became industry enablers for 248 and then 193 nm lithography.  I think it was only two years after the founding of Cymer when they shipped their first excimer light source.  The development of the EUV light source was also directed by Sandstrom, though it took a bit longer!  These light sources have always been critical to the success of Moore’s Law and lithography’s role in it, and Richard’s contribution for over 30 years was seminal.  Congratulations!

It was good to welcome Todd Younkin back to this conference.  He abandoned the field of lithography after ten years at Intel to become the CEO of SRC (Semiconductor Research Corporation), and his talk focused on SRC’s role in charting a sustainable future for semiconductors.

The industry giant Gordon E. Moore died last March at the age of 94.  His influence on the lithography community was profound (his insights that became Moore’s Law, the founding of Intel, even his 1995 plenary talk at this conference) and so the symposium decided to remember him with a very special Tribute Session.  Harvey Fineberg, President of the Gordon and Betty Moore Foundation, gave a video speech about his ongoing legacy of charitable contributions.  Craig Barrett, former Intel CEO, provided many moving stories about his times with Moore, and their joint love of fishing.  A main theme: while a very quiet man, when Gordon Moore spoke, people listened.  Paolo Gargini, former Director of Technology Strategy at Intel, provided a personalized history of Moore’s role in Moore’s Law (in classic Gargini style:  80+ slides in 20 minutes).  Dan Hutcheson of Tech Insights described Moore as a “gentle giant” that believed in the fundamentals.  Dan provided my favorite quote of the day: “Moore’s Law is about us and our ability to innovate.  It is not a law; it is an opportunity.”  Finally, Burn Lin and Martin van den Brink tied Moore’s Law to our community by giving each their own take on the history of lithography.  It was a great tribute.  (Aside: the announcement of Martin van den Brink’s imminent retirement from ASML provoked a standing ovation for his contributions to our community.)

The regular conference talks began in the afternoon, and I started with an invited talk by Andras Vladar (NIST) commemorating the 40-year anniversary of the first CD-SEM (introduced by Hitachi in 1984).  I agree with him when he said there are no low hanging fruits for improving SEM technology, but there are fruits.  The future of SEM technology in the semiconductor industry “is bright.”

The end of the talks on Monday is always a highlight for me, since it marks the beginning of the Fractilia Happy Hour – thanks to everyone who came!

SPIE Advanced Lithography and Patterning Symposium 2024 – day 0

The 2024 SPIE Advanced Lithography and Patterning Symposium is 6 conferences, 3 plenary talks, 1 special session, 2 panel sessions, 15 short courses, and 1 poster session, and it starts Monday in San Jose, California.  Abstract submittals were 215, about the same as last year, and registration is up about 15% from last year, to 2,200.  That is right at the historical average for the ten years prior to Covid.  It is good to be back!

I am beginning the week relaxed, for a change.  For more than 30 years I have spent the Sunday before the start of the conference teaching an eight-hour short course (and for some of those years, 12 hours).  I love to teach, but I am not as young and energetic as I used to be.  Standing and talking all day is exhausting, so finally I decided that is not how I wanted to start my week.  Instead, I took a class!  (Thank you, Ofer Adan, for a great course on metrology tool matching.)  So as Sunday comes to a close, I am relaxed and ready for any exciting week discovering what is new in lithography, patterning, metrology, and more.

SPIE Advanced Lithography and Patterning Symposium 2023 – day 4

I began the last day of the conference at the EUV talks.  Jo Finders of ASML described how non-idealities of the scanner can effect single-layer edge placement errors (a combination of CD errors, both global and local, and local pattern placement errors).  This was the first time I had seen a numerical breakdown of mechanisms of “NILS loss”, the reduction of the Normalized Image Log-Slope from its theoretical value caused by mask topography, aberrations, flare, focus variation across the slit, etc.  The NILS loss totaled to 15%, and Jo described various approaches to get some of that back.

Suk-Koo Hong of Samsung provided “speculations” on why pushing k1 below 0.4 in EUV is problematic (specifically, for printing contact holes).  The reason is stochastics, and there seems to be a scaling with pitch and CD that is worse than the famous z-factor predicts:  z-factor = feature size^3 * LCDU^2 * Dose-to-size.  Plotting LCDU (local CD uniformity) versus dose produces higher than expected LCDU at the lowest doses and seems to be following a different iso-z-factor limit.  The specifics of CD and pitch and anything else that made up the data points in his graphs, however, were not revealed.  Still, it was an interesting way to look at the problem, one still without a solution.

As an aside, Samsung gave many papers this week, and some of those papers were some of the best in the conference.  Case in point: Hyungju Ryu presented work by Sangjim Kim (who couldn’t make it here) on process control for EUV metal oxide resists (MOR, read Inpria).  The two MOR challenges are CD variation due to sensitivity to humidity, and poor etch resistance.  Apparently, these problems are well known to the users of Inpria resists, but they weren’t being discussed publicly until now.  For example, CD was shown to vary by 2 – 8% depending on the post-coating delay.  Samsung showed, however, that careful optimization of every resist processing step reduced the CD variation to 35% of its original value.  Etch resistance of the MOR was not as good as expected since partially exposed resist does not have a well-connected network of core-to-core bonds necessary for best etch resistance.  Samsung’s solution was a UV flood exposure.  They said that more work was required to make the MOR ready for high volume manufacturing, but these were good steps in that direction.

On a completely different topic, Etienne Poortere of ASML showed how a carefully designed test mask coupled with voltage contrast metrology could be used to establish design rules for via connections to metal 1 in a dual damascene process of 28 nm pitch.  The technique made evaluation of a matrix of tip-to-tip spacings and M1 via overlap rules quite easy.

Back in the SEM world, Ofer Adan gave a good marketing talk on Applied Materials’ new cold field emission (CFE) electron source for their inspection SEMs (and maybe for the CD SEM?  It wasn’t clear.).  I’m convinced this new CFE source is better, but I don’t know why.

As is usually the case, by Thursday afternoon my brain had reached its absorption limit.  I continued going to talks, but my notes became brief as my attention strayed.  Summing up, this week lived up to my expectations – it was the Advanced Lithography and Patterning conference back to its full glory.  There were many solid talks – nothing earth shattering (but there rarely is), just good incremental progress towards the harder to reach goal of keeping Moore’s Law alive.  It’s a shame that the memory sector downturn kept many Micron and SK Hynix lithographers away, and that Intel’s troubles kept their attendance to a minimum.  It was gratifying to see so many good papers from Samsung, and decent attendance from TSMC.  I go away looking forward to next year.

SPIE Advanced Lithography and Patterning Symposium 2023 – day 3

Bright and early, the talks begin at 8:00 am.  From Mark van de Kerkhof of ASML, and then Joost Bekart of imec, we got two updates on EUV pellicles.  The composite (metal-silicide) pellicles are the second-generation pellicle after polysilicon, but they are stalling out with transmission near 90%.  Higher transmission requires thinner pellicles, which is quite difficult.  The low transmission also limits the highest power that can be used (absorption heats up the pellicle, and if the heat cannot be removed fast enough the temperature rise will ultimately destroy it).  Slow progress can be expected, but it seems that increases in source power will outpace increases in transmission.  That is why the carbon nanotube (CNT) pellicle, first proposed by imec in 2015, is so interesting.  It has extremely high transmission (> 97% after being annealed to remove contaminants) and so can withstand very high source power (> 1000W).  It’s drawback is the gradual thinning of the pellicle with use as the carbon (activated by all the EUV light) reacts with hydrogen gas, which ASML puts in the system specifically to remove carbon deposits that might occur inside the tool!  An interesting dilemma, and I will enjoy watching progress towards a solution.

Back in the metrology session Yoshihiko Fujimori of Nikon introduced a new tool for high-density CD measurements on the wafer.  The paper was sparse on some important details, but the tool reminded me of a crystallography setup, measuring the diffraction pattern of the whole patterned wafer with variable wafer and detector angles.  (The name AMI-5700, along with a marketing picture, indicated at least close to commercial readiness.)  A full wafer, up to 100,000 points, can be measured in a couple of minutes.  That means about a 1 mm spatial resolution, and it is obviously limited to periodic structures (and so memory chips).  The key idea appears to be correlating various “signals” coming from the detected diffraction pattern with SEM-based measurements of CD in a previous calibration step.  Then a measurement of that signal across the wafer is used to infer CD variation across the wafer.  Like all such techniques, the two key questions are sensitivity to noise, and sensitivity to other systematic variations (such as an underlying film thickness) that might also impact the signal being monitored.  These problems have bedeviled other similar attempts in the past.

Gian Lorusso of imec gave a fast-paced overview of the metrology of thin versions of the dry Lam Research resist.  As Gian has shown in the past, low signal-to-noise ratio CD-SEM images that often result from very thin resist patterns can make accurate metrology difficult (even when using state-of-the art metrology software from Fractilia!).  The main message from this paper is the happy fact that the Lam dry resist offers fairly high material contrast in the SEM, making measurement of even 10 nm thick resist patterns acceptable at normal SEM settings (such as 16 frames of averaging).

On the topic of resist shrinkage in the CD-SEM (a problem that never goes away, no matter how much we ignore it), Musaki Sugie of Hitachi offered an interesting combination of ideas.  As many SEM vendors have demonstrated, going to 100 V reduces shrinkage, though it increases the noise in the image.  (Ran Alkoken of AMAT showed their 100 V CD-SEM in the following talk.)  This voltage was coupled with an optimized scan speed to minimize charging and to prevent CD measurement repeatability from suffering.  An interesting additional idea in the talk was to average together 32 sub-sections from a large 1-frame image of lines and spaces to measure CD with the precision of a 32-frame image and the shrinkage of a 1-frame image.  Information such as linewidth roughness or local CDU cannot be obtained, but for the one goal of finding the CD with minimal shrinkage, the approach may work.  As an aside, he noted that metal oxide resist (that is, Inpria) has 3X less shrinkage than chemically amplified resists for EUV.

After lunch I saw a few papers from imec, updating prior efforts.  Andreas Frommhold used Mark Maslow’s concept of Tail CD (measured mean +/- 3sigma of the contact hole distribution) as a predictor of merged contact hole rates.  In this case, the CD being measured was the gap between the holes, and the mean – 3sigma value is correlated with rates of merged holes.  I know from experience, however, that exactly how one defines and measures this hole-to-hole gap CD is quite critical.  Lieve Van Look of imec continued her very detailed work on local MEEF (mask error enhancement factor) and its impact on LCDU, bringing the concept of MEEF into the era of stochastics.  Her collection of papers on this topic so far represents the definitive work on the topic.

The poster session in the evening was, thank goodness, in a massive hall with plenty of room to work your way among the posters without being jammed in by the crowds (which frequently happens at other conferences).  Alas, being a long-time participant in this conference meant that my mean free path (the average distance traveled before running into someone to talk to) was very small.  I didn’t see many posters.  For all the poster presenters out there – please turn in a manuscript of your paper so I can read them!

SPIE Advanced Lithography and Patterning Symposium 2023 – day 2

(This post is certified ChatGPT-free.)

The day began with a second plenary, starting with ASML/SVGL/Perkin-Elmer veteran Chip Mason describing the history of the first commercial projection lithography tool, the Micralign, on the occasion of its 50th birthday.  I am very sorry to say that another commitment prevented me from attending Chip’s talk, but numerous people (young and old) told me that it was fantastic.  My first job as a lithographer (exactly 40 years ago this month!) involved supporting a fab with both a Micralign 300 and an Optimetrix 10X stepper, so the importance of the Micralign is also a bit personal for me.  (Steppers were introduced five years later, in 1978, but the Micralign remained the workhorse of the industry well into the 1980s.)  But not only did we hear about the Micralign, we get to see one.  ASML now owns the former Perkin-Elmer site in Wilton, Connecticut where the Micralign was developed and manufactured, and they managed to find a Micralign in a garage somewhere (Vermont, I believe).  The owner donated the tool and ASML had it shipped to San Jose where it is now on display (for one more day) in the Exhibitors’ Hall.  Seeing a Micralign 300 in person is a wonderful opportunity.

Micralign 300 by Perkin-Elmer
Micralign 300 by Perkin-Elmer on display at the SPIE Advanced Lithography and Patterning Symposium

Attending papers on Tuesday morning had me bouncing between sessions, as usual.  Rudy Peeters of ASML gave an update on the readiness of high-NA EUV tools, including the status of the the four major components of the tool (source, reticle stage, wafer stage, and projection optics).  Three EXE:5000 sources have been qualified (benefiting from commonality with sources from the low-NA tool), four wafer stages have been built (and are working towards testing at full acceleration), and one reticle module was built and is being tested.  Multiple mirrors have been made, and so the next major milestone to watch for will be the first working projection optics box.  It is fun to hear ASML express their optimism as if it were established fact:  the goal of the high-NA EUV tool introduction in 2025 is to “replace EUV double patterning.”  It is also interesting to infer the market ambiguity of this tool from statements like “high contrast imaging can be used for better images or better dose.”

Greg Denbeaux of SUNY Polytechnic (Albany) gave a very nice talk on attempts to move the idea of polymer aggregation as a source of resist stochastic variability from speculation to experimental measurement.  By printing an open-frame EUV exposure at the dose to clear, residual resist at the substrate can be measured with an AFM to get some feeling of the size of the clumps of resist there.  I wouldn’t call the method exactly quantitative, but it is a start.

Yaniv Abramovitz of AMAT looked at using in-device overlay measurement by a SEM at ADI (after develop inspect) rather than the traditional AEI (after etch inspect) measurements, and compared them to optical scribe-line measurements.  His results from the classical skew experiment (where the scanner is directed to purposely offset the stage position of the second layer in increments, and then the measured overlay is plotted versus this scanner input skew) yielded unexpected slopes far less than 1.  How could this be?  Scanners have incredibly accurate stage positioning.  AMAT has some more work to do.

Overlay and the role of stochastics in edge placement error (EPE) is my new special interest, so I spent the rest of the morning and much of the afternoon in sessions on those topics.  Myungjun Lee of Samsung gave a fascinating talk on their development of hyper spectral imaging reflectometry for massive overlay and CD measurements.  The traditional OCD (optical CD) approach collects reflected spectrum (reflectivity versus wavelength at a fixed angle) using a modest spot size (20 – 100 microns) aimed at a target of regular patterns (usually lines and spaces of fixed pitch).  Analysis of the spectrum yields measurement of the CD, and possibly other information about the features.  Spectral “imaging” reflectometry shrinks the spot size (to about 5 microns in this case) and uses that spot as one pixel in a larger “image” of many pixels.  It is only an image in the sense that imaging optics are uses to collect data from each pixel in parallel, so that this technique is essentially massively parallel OCD.  How massive?  3200 x 3200 pixels covering a 20.8 mm x 20.8 mm field.  The massive data that can result from this tool opens up many interesting use cases.  It is my understanding that Samsung is looking for an equipment partner to commercialize the technology.

Several authors (starting with myself the day before) described how EPE measurements are best used as an input to a calculation of yield (or number of good die).  Inho Kwak of Samsung showed that using a prediction of number of good die (generically called a KPI = key process index, in the jargon of the fab) during advanced process control (APC) resulted in a 5% improvement of dies in spec.  The control strategy first suggests an adjustment of the dose of the second layer, then calculates the overlay correctables to achieve lowest EPE (rather than individually trying to match CD with dose, then overlay with the correctables).  Harm Dillen of ASML and Franz Zach of KLA proposed similar approaches.

In the SEM measurements session I especially like John Villarrubia’s talk on three new SEM-based fundamental research projects at NIST.  John is the author of a standard Monte Carlo simulator for SEM behavior called JMONSEL, and these new projects aim to fill in some gaps and improve the accuracy of this simulator.  The first experimental piece will compare a top-down SEM image at low voltage to a STEM (scanning transmission electron microscopy) image at high voltage for the same sample and in the same instrument.  The second experiment measures secondary electron yield of materials, with the benefit that the materials are deposited and then measured without exposing the films to the atmosphere.  The third project seeks to improve the models in JMONSEL using the data from the first two projects.  This is a very worthwhile activity, and I commend John and NIST for taking a leadership role in these investigations.

The last talk I attended was also one for which I was a coauthor.  Genevieve Kane of IBM gave her first SPIE presentation – congratulations on a nice job!