The 3-beam conference here in Las Vegas began on Wednesday morning with the plenary session. Nick Economou discussed the history and current performance of the Helium Ion Microscope. What an amazing tool! It has much higher resolution than a scanning electron microscope (SEM) with far less charging. The result is truly amazing pictures of biological and other non-conducting samples. I can’t wait to see pictures of photoresist patterns with this tool – I’m sure it will quickly become indispensible, especially for line-edge roughness characterization.

Sam Sivakumar of Intel seems to be making a second career out of giving plenary talks (proof of the never-ending interest in hearing about what Intel is going to do next). His talk brought up a long-simmering (or at least recently-simmering) question that I have. Standard naming convention for semiconductor technology nodes cuts the name of the node in half for two generations out. Thus the 90-nm and the 65-nm nodes become the 45-nm and 32-nm nodes (sometimes rounding is necessary). Of course, these names have nothing to do with the dimensions of the features involved in the process, but the standard of dividing by two for the names has seemed inviolate. Today most state-of-the-art companies claim to be manufacturing at the 32-nm node. That means two nodes out would be the 16-nm node, right?

So I didn’t know what to think when Intel began calling it the 15-nm node. Why? Are they hoping for a 1-nm marketing advantage over their rivals? If they don’t get to the node first, will they say “Yes, but they are only doing 16-nm, but WE are doing 15”? A 1-nm advantage seems insufficiently significant, and now it seems that the marketing gurus at Intel agree. While the program listed Sam’s talk as having “15nm Node” in the title, his opening slide had changed the title to “14nm Node”. Now Intel will have a 2-nm advantage over the rest of us. That’s real progress.

Sam provided a couple of quotable moments in his talk: “Traditional scaling approaches will no longer work.” “Fundamental work is needed in LWR to affect improvement.” I agree.

Matt Malloy of SEMATECH gave an interesting talk on the sources of defects for nanoimprint lithography (of the Molecular Imprints step-and-flash variety). This is an important topic since defect density is the only serious roadblock to implementing nanoimprint in production. I was surprised to learn that the vast majority of defects come from the template manufacturing process. At least we know where to focus our attention now.

I was happy to hear from Dan Sanders of IBM Almaden Research that directed self assembly (DSA) has moved past the “trough of disillusionment” in the Hype Cycle and is now entering the “slope of enlightenment”. Progress on DSA in the last year has been remarkable, and I expect that progress to accelerate in the next year. This is a research area to get behind.

David Melville of IBM gave an invited talk on computational lithography. This quote was right on: “Effective optimization [of the total lithography process] is no longer in the realm of the lithography engineer.” Serious mathematicians and computational geeks are needed as well. What a different world from when I started computing lithography on my PC so many years ago.

A cool idea that I am still learning about is “Absorbance Modulation” materials. Essentially, they are like the old idea of contrast enhancement materials, but made erasable using a second wavelength of light (one that the underlying resist is not sensitive to). There are many variations on how such a material can be used to improve resolution, but the real goal would be to perform double patterning with just a double exposure process. Alas, no absorbance modulation materials are yet available at 193 nm.

On the last day of the conference I gave my paper – a work completed that morning and something completely different from what I had originally proposed in my abstract. That’s life on the (rough) edge of research.

The Mapper folks had a couple of talks promising a 1 wafer-per-hour maskless e-beam lithography tool by the middle of next year. If they succeed, that tool could be a game changer. I’ll be staying tuned, but the challenges remain great.

Finally, at the end of the day Alex Liddle of NIST had a fascinating talk on measuring acid blur in chemically amplified resists using single molecule fluorescence. Cool stuff, though more work is needed.

Another interesting 3-beams conference is over, and I can hardly wait for next year’s conference. I doesn’t hurt that it will be on the Big Island of Hawaii in 2012.

Aside: Thanks to Richard Blaikie for exposing me to this quote from Albert Einstein: “Any intelligent fool can make things bigger, more complex, and more violent. It takes a touch of genius – and a lot of courage – to move in the opposite direction.” This could be the motto of lithographers everywhere.

Las Vegas is not my favorite city. It is America’s monument to greed (and bad taste), where form not only wins over substance, it’s as if substance never even showed up for the race. This place relishes in its lack of roots, tearing down old facades to build newer, bigger facades (little is more pathetic than faded glitz) in an arms race of extravagance. It is all so purposely disorienting.

So why am I here? It is time for the 55th International Conference on Electron, Ion and Photon Beam Technology & Nanofabrication (EIPBN). That’s a mouthful, which is why attendees universally call it the triple-beam or three-beams conference. Fortunately, the conference is in a resort near the mountains outside of town. Still, even this place will not let you escape the Las Vegas vibes – you can’t get anywhere in the resort without walking through the smoke-filled Casino that fills its core. Ah well.

I don’t attend this conference every year, but I wish that I could. It is generally academic, with papers that are a shotgun blast of ideas ranging from cool to bizarre. I always come away inspired and with new things to think about and work on. That will be my way of judging success this year as well.

The conference will begin with a plenary session, but the festivities have already started with the traditional Tuesday evening welcome reception, this time including an Elvis impersonator. Welcome to Las Vegas.

Dr. Steven A. Orszag, a renowned expert in computational fluid mechanics, died on May 1 at the age of 68. (His obituary in the New York Times can be accessed here.) One of his most important contributions was the development of spectral methods for solving complex fluid dynamics problems, greatly increasing the efficiency of the numerical calculations. These techniques are now standard in fluid dynamics, especially for turbulent flow, but are also used in a number of other applications of scientific computation.

It is one of those other topics that caused me to meet Steven. Dr. Orszag had a long collaboration with Dr. Eytan Barouch, of Clarkson and then Boston Universities. Eytan got involved in lithography simulation in the late 1980s (I worked with him quite a bit during those early years) and applied Orszag’s spectral methods to aerial image simulation problems. Eventually Barouch and Orszag formed Vector Technologies to market their lithography simulator FAIM. Orszag’s involvement was mostly advisory and on the technical side, so far as I could tell. In the 1990s Dr. Orszag was the coauthor of 16 SPIE proceedings papers on lithography simulation, and I met him a time or two at these conferences. Obviously bright and busy, it was clear to me that lithography was more of a hobby to Dr. Orszag, an interesting offshoot of his many scientific interests.

Steven Orszag also has a famous son – Peter Orszag, formerly the budget director for the Obama administration.

This week in San Jose began cold, but warmed up by Thursday to the kind of weather we all expect from California. So too with the conference, and I think Thursday had some of the most interesting, and surprising, presentations.

The day began for me with the much-anticipated presentation by ASML on the NXE:3100 extreme ultraviolet (EUV) “pre-production” lithography scanner. As expected, it was by parts marketing pitch, pep talk, and soothing reassurance that everything is under control. The first of six NXE:3100s shipped to Samsung last year, printing its first wafers in December. The second 3100 is being installed now at Imec in Belgium. The other systems will roll out in about two month intervals. Unfortunately, there was no official word (or data) from the system as running at Samsung, but ASML provided a good overview of the performance of the systems at the ASML factory.

You have to give ASML a lot of credit – they know how to build a good tool. The lens quality, resolution, defectivity, and overlay performance was as good as anyone could expect as this point. The “tool flare” was down to 5%, but be careful – the total flare seen at the wafer is the tool flare plus flare caused by the mask and REMA masking blades. This total flare is chip-layout dependent, and was as high as 12% for a Flash chip example they showed (you had to be very close to the screen to see the small “12” in the legend of the graph, but at least it was there).

The performance of the tool was very good, except for two problems. The linewidth roughness (LWR) of all their images was very bad, though not a single LWR measurement was shown in the presentation. But it was the throughput that everyone was most interested in hearing about, and that number was 5 wafers per hour. Of course, that is not a “production” throughput number, since it assumed a 10 mJ/cm2 resist and didn’t expose any edge fields, but it’s still a benchmark number to compare to. It’s better than I thought it would be, but still a factor of 12 from the tool spec of 60 wafers per hour. ASML sought to reassure the skeptical members of the audience by renaming their roadmap for source power an “upgrade path” instead.

As anyone who has known me for a while already knows, I am a skeptic of the viability of EUV lithography for IC manufacturing. It’s not that EUV can’t work, it’s just that the effort required to make it work doesn’t line up with the timing and cost needs of chip manufacturers. When serious work first started on EUV lithography in the mid 1990s, the target insertion into manufacturing was the 130-nm node. Since then, the target has slipped by at least two years for every three years of effort. Today, Intel talks about inserting EUV into manufacturing at their 10-nm node four years from now. The result: tool development has been shooting at a moving target, which is almost always a recipe for disaster.

The 10-nm node for logic means a 20-nm or 22-nm half-pitch, which puts the k1 factor for the half-pitch below 0.5 on the (newly increased) 0.33 NA production tool. This means off-axis illumination will likely be required, and it will be difficult to extend the tool to the next node. Mask blank and patterned mask defectivity is still an unsolved problem, and thanks to a lack of appropriate mask inspection tools we “don’t know what we don’t know” in terms of how bad the problem is. Cost, of course, is just as critical as performance, and a $100M tool will need at least 100 wafers per hour in production throughput (spec’ed throughput much higher) to be viable. The effort required to get beyond 100 wafers per hour is huge, especially since the exposure dose constraints that LWR will put on the resist are not likely to be overcome. We have no roadmap, let alone on upgrade path, for reducing LWR to 2 nm.

And so the final push is on. It will be an all-out effort by the industry for the next 12 – 24 months to try to make EUV lithography work. But ASML has 10 production EUV tool orders in their hands. How did they manage that, given the uncertainty involved and the fact that the preproduction tool has yet to be evaluated? As one chip maker told me, ASML is very good at “twisting arms”. Another chip maker said they had no choice but to “play the game”. After all, ASML controls the spigot on 193-nm immersion tools. So the orders are in, and the industry is sharing the risk with ASML (probably not a bad thing). If this year at the SPIE Advanced Lithography Symposium was interesting, next year promises to be even more so.

To make it clear, I am a skeptic, but I would be happy if EUV lithography was successful. I’m doing my part by trying to understand the fundamentals of LWR. Regardless of the outcome, the EUV effort is fun science and engineering! I hope we will continue to work on the hard problems of EUV in the cold light of reason.

The most pleasantly surprising aspect of this year’s symposium was the variety and quality of work presented at the Alternate Lithographic Technologies conference. Now that EUV has been separated out as its own conference, the Alternate Lithography conference has been able to flourish with exciting presentations on nanoimprint, directed self-assembly, interferometric lithography, and many other innovations. The University of Wisconsin had a great talk on modeling self-assembly. Virginia Tech surprised me with a novel (and potentially revolutionary) approach to double patterning as a non-linear double exposure. And it is always fun to think about the bizarre behavior of evanescent waves, inspired by a very good talk from the University of Canterbury (Christchurch, New Zealand).

And now I’m going home, where I hope to catch up on the sleep I’ve lost in the last week. Am I getting too old for life in the fast lane of advanced lithography?

Today I talked more than listened. I had two papers, both on stochastic effects in lithography. In one, I showed a complete model for EUV resist exposure and for predicting stochastic uncertainty in the acid concentration at the end of exposure. The second, looking at quenching effects, is unfortunately a work in progress. There is still much to learn. One important lesson is to get my papers done before I come to the conference.

But since I am on the topic of learning about line-edge roughness (LER), I have been very disappointed with the number and quality of this year’s papers on this topic. I’ve said it before and I’ll repeat it here – it is my opinion that line-edge/linewidth roughness (stochastic effects in general) will be the ultimate limiter to resolution in optical lithography. We are already nearing that point, with many at this conference talking about how great some experimental result is “except for the roughness”. From what I can tell, there has been essentially no progress in improving LER since last year, and insufficient progress in improving our understanding of LER mechanisms.

As for LER metrology, I can’t tell whether the metrology is not good enough, or whether metrology users are just unwilling to do it right. Doesn’t anyone realize that measuring noise is inherently noisy? If I measure LWR to be 5 nm, using a typical 128 measurement sample on one image, the 95% uncertainty just from random error is +/- 12%, that is 5 +/- 0.6 nm. I did not see more than one paper that put error bars or uncertainty estimates for LWR in their presentation. I saw several talks that presented LWR values to two decimal places, or showed materials that exhibited 5% lower LWR, without any discussion of the statistical significance of the numbers. Aren’t we engineers and scientists here? We can do better. Samsung gave an interesting talk showing how their measured LWR varied from 3.1 nm to 5.4 nm on the same sample just based on their measurement recipe. Systematic errors on top of the random errors.

And since I’m riled up, let’s talk about LER post-processing, AKA magic rinse. This is where a rinse or vapor or e-beams or ion beams, usually with some heat, is used to smooth out the roughness of the sidewalls of resist. I’m sorry, but this just won’t work. Low frequency LWR is a linewidth error. A rinse can’t remove linewidth errors from the resist (if it does you have even bigger problems to worry about), so it can only remove the high-frequency roughness that doesn’t really matter any way. It’s like using a rinse to remove my gray hair. It might make me prettier, but it won’t make me a nice guy.

OK, I’m off my soap box.

I spent much of Tuesday learning about alternate lithography schemes. Toshiba gave an update on their efforts to evaluate nanoimprint lithography for chip manufacturing. The technology is closer to prime-time than I expected. Most of the data for 28 nm half-pitch looked very, very good (CDU of 1.2nm, LWR of 2nm, mix-and-match overlay of 10nm), but of course there is one big problem remaining. Mask defectivity is a factor of 100 too high. Toshiba has given themselves one year to bring defect densities down. I wish them luck.

The technology that has excited me the most this year is directed self-assembly (DSA). Several authors have presented phenomenally good 25-nm pitch line/space patterns. This stuff is cool! There are still many things to learn (and to fix) about the technology, but the potential is so great that there is no doubt the industry will aggressively pursue DSA in the next few years. The progress has been very rapid. My favorite quote is from Chris Bencher: “DSA can not be ignored.”

Many people told me there was a lot of buzz around multi-beam electron beam technology. I didn’t see any of the papers (the curse of parallel sessions), but the technology is generating interest. Not everyone is a believer in EUV.

But many people are believers. The EUV conference this year has the most papers of any conference. The bulb glows brightest just before it burns out. But more on that topic later in the week.

The SPIE Advanced Lithography Symposium always begins on Monday, unless you take (or teach) a short course the day before. Only 12 courses are being taught this year, a low not seen this millennium and indicative of austere times. Still, short course attendance was up a tiny bit, and my course was full, and as always was fun to teach. I had two young engineers from Egypt in my class, and when I congratulated them on recent events in their country, the class broke into spontaneous applause in solidarity. Nice.

There are 567 papers at the conference (and in this year’s most inane statistic, 8.5% of the authors are from Texas). Attendance at the symposium is up about 10% – a good sign, though we are still way down from our peak of 2007. I suspect those heady days will not return. But the crowd is energetic, with passions, excitement and doubts about the future of lithography alternating in about equal measure.

Monday began with awards at the plenary session. It was great to see Andy Neureuther, (mostly) retired from UC Berkeley, receive the 8th Frits Zernike award. Andy’s first paper on lithography simulation was published 40 years ago, and his body of work has been a tremendous influence on me. Four new SPIE Fellows were inducted, and I was ecstatic to see my dear friend John Petersen so honored. Bob Socha of ASML become our youngest Fellow, though thankfully he is not as young as he looks.

The two plenary talks were two sides on one coin: why more Moore’s Law is more goodness. Luc Van den Hove, the President of CEO of Imec (and someone who once gave papers at this conference – a long time ago) said more Moore would make the world a better place. I’m not sure that his example of an electronic nose for smart phones convinced me. He also didn’t convince me when he said, discussing lithography alternatives, that “EUV lithography is the more developed, more mature technology.” But then, Imec has always been a cheerleader for their Dutch neighbors.

Shang-Yi Chiang of TSMC gave a more grounded plenary talk, saying more Moore meant more money. He is hoping for EUV lithography at the 14-nm node, but only if the throughput is >100 wafers per hour. He reiterated what we all already know, that lithography cost is the biggest challenge to extending Moore’s law through the rest of this decade. Which is why no one likes double patterning (though everyone is doing it). While Chiang struck an agnostic tone about various lithography alternatives, he put on his cheerleader hat to talk about 450-mm wafers. He is hoping to find various governments that will put up $750M over the next three years to induce tool makers to develop 450-mm tools. Even if we find the money (and good luck with that), I think this is a lost cause. How about this for a fanciful thought: imagine a 450-mm production EUV lithography tool.

By 10:30 am the technical talks began. Patrick Naulleau discussed the challenges of EUV resists and lamented that EUV resist resolution has been stuck at 20-nm lines and spaces for the last three years. This doesn’t surprise me, since we haven’t had a new EUV exposure tool in the last three years. We shouldn’t expect a magic resist to make up for a lack of tools. Jim Thackeray said there is still room to improve EUV resists (as of course is true). At 193-nm we worked hard to make our resist more transparent, but at EUV we are trying to make them more absorbing (every photon is precious, and unabsorbed photons are wasted photons). Teflon has the kind of absorption we need, so know we just need to figure out how to make our resists more Teflon-like. Roel Gronheid of Imec gave a great talk, showing what I thought was a very convincing demonstration that secondary electron blur in EUV resists was less than 4 nm. One less thing to worry about, since none of us know how to reduce this source of resist blur.

(By the way, for those of you wondering why my posts are running late this year, I can only say this. I have three oral papers to give, and only one is ready.)

In the long view, one thing is clear: the remarkable success of optical lithography at propelling Moore’s Law forward has been a long, steady ride. Moore’s Law has been lithography-limited since the early 1970s, so the steady progress in Moore’s Law over the last 40 years mirrors the steady improvement in resolution that optical lithography has been able to deliver in manufacturing.

But while the results of lithography seem to improve at an astonishingly steady pace, the path to get there has been anything but smooth. There are three big trends driving the improvements in resolution: lowering the wavelength of the imaging light, increasing the numerical aperture (NA) of the imaging lens, and being more clever at squeezing every bit of resolution that physics will allow (including the manipulation of the angle, phase and polarization of the light, as well as significant improvements in the performance of the photoresists used). Let’s look at each trend in more detail.

Lowering wavelength is an obvious way to improve resolution, but also a difficult one. A change in wavelength requires a change in the light source, the lens materials, and the photoresist – that is, almost everything. Since the early days of 436-nm light, we have steadily progressed to 365 nm, then 248 nm, and today’s standard 193 nm. Each change was extremely difficult, but ultimately rewarding. Lithography companies were born and were lost in the transitions. But the story is not quite so linear. The industry spent a fair amount of time and money to develop 157-nm lithography, only to abandon the effort as not worthwhile. And before that a major industry (and government) investment in x-ray lithography become a major failure (and a running joke among lithographers – will the new technology be our savior, or the next x-ray?). Today, the focus is on a another disruptive change in wavelength – to the 13.5-nm wavelength of extreme ultraviolet (EUV) lithography (the wavelength formerly known as soft x-ray). The outcome of that effort is yet to be decided.

Numerical apertures have risen from the Perkin-Elmer Micralign’s 0.16 to today’s best 1.35 (NAs great than 1 required the development of immersion lithography, an absolutely amazing technology). But 1.35 appears to be the limit. An effort to develop high refractive index lens and fluid materials was deemed too difficult and was dumped a few years ago. There’s no more room at the top.

Innovations like phase-shifting masks and off-axis illumination have coupled with significant improvements in photoresist performance and manufacturing process control to allow practical resolution to approach the theoretical limits. While I’m sure there are still innovations to be had (not to mention the dozens of interesting ideas that have been left behind), current performance is so close to the best that physics will allow that there is very little room left to squeeze.

Oh, and by the way, this forty years of (sometimes rocky) progress in resolution has come at no extra cost to make the chips (the cost per square centimeter of finished silicon has stayed about constant for 40 years). Improved yields, larger wafers, and much greater lithography tool throughput has meant that today’s US $50 M lithography scanner can still churn out chips that can be profitably sold for on the order of $10.

So what’s in store for the future of lithography? The only current effort that has the potential to keep us on track using the traditional three scaling approaches is EUV lithography. But the challenges for EUV are still immense, and I remain skeptical. An alternate path is the use of double patterning (or quadruple patterning!), but there the higher costs may prove limiting. This technology is now widely used for making Flash memory chips, but the extension to logic chips is hard.

It is an interesting time in the world of lithography technology – and progress in developing the next bit of technology will be anything but predictable. Companies are beginning to place their bets on competing approaches, and the certainty of success is low. And looming in front of us is possibly the ultimate physical limit: line-edge roughness caused by the stochastic nature of light and chemicals near the molecular scale. It’s fun, and frightening.

But there is one thing everyone in the lithography community agrees on: the place to go to follow the latest progress in the field is the SPIE Advanced Lithography Symposium, which starts Monday in San Jose. How far has EUV lithography progressed? How big are the remaining roadblocks? What innovations in double patterning might make this approach more practical? Has anyone made any progress in reducing line-edge roughness? I’m anxious to learn the answers. That’s why I’m here.

I’m excited to announce my recent appointment as editor-in-chief of SPIE’s Journal of Micro/Nanolithography, MEMS, and MOEMS (effective 1 January 2012). I’ll be taking over from Burn Lin, the founding editor whose vision built this journal into the preeminent peer-reviewed publication on micro- and nanofabrication. Big shoes to fill. With help from the lithography, MEMS and MOEMS community, I hope to build on an already excellent foundation.

To read the SPIE press release on this appointment, click here.

Have you ever been reading through my textbook Fundamental Principles of Optical Lithography and thought “Boy, if I only had a set of Matlab exercises to do, I could really learn this stuff!”? Well if a laboratory manual full of Matlab problems is the only thing keeping you from learning optical lithography, your wait is over! Kevin Berwick of the Dublin Institute of Technology has been teaching a lithography course using my textbook and has been assigning Matlab problems to his class to help them get at the details of the topic. He has now collected up those problems and published a book called Optical Lithography Modelling with MATLAB®, Laboratory Manual to accompany Fundamental Principles of Optical Lithography, by Chris Mack. And if that is not enough to put any lithographer in a good mood, this book is available to be downloaded free! Click here for more information. A great Christmas present for that hard to shop for lithographer!