The second plenary session began with the announcement of the new SPIE fellows from our community: John Fourkas of the University of Maryland, Doug Guerrero of Brewer Science, Seiji Nagahara of ASML, and Eric Panning of SiClarity.  Congratulations!  There was also a tribute to Bob Dennard who died last year.  Dennard of IBM was the inventor of the single-transistor DRAM and the developer of “Dennard Scaling”, the CMOS scaling rules that formed the explanation for why Moore’s Law worked so well for so many years.  I loved this quote from him: “If you want to be successful, attitude is everything.”

The first plenary talk was by Christophe Fouquet, the new President and CEO of ASML.  Unlike the previous CEO, Christophe is a technical guy, coming up through the engineering ranks of the semiconductor industry at Applied Materials and KLA before going to ASML.  It was nice to have him speak to this community directly.  He showed an example of why Moore’s Law keeps going despite all of the difficulties:  we keep redefining Moore’s Law.  His plot of Number of Transistors per year (on a log scale) now shows the number of transistors per package rather than per chip.  He described the power problem also mentioned by Shien-Yang Wu, that the power used to train AI models is growing 10X per year, a completely unsustainable trend that must end in the next one or two years.  One possible solution is Processing in Memory, putting CPU-like capabilities on the DRAM chip (which has the added advantage of being 16X faster).  This idea has been around for a long time but resisted since it makes the DRAM part of the chip cost about as much per unit area of silicon as the CPU.  This crazy idea (increasing the cost of your memory by an order of magnitude or more) doesn’t seem as crazy in the era of $1000+ Nvidia chips.

Nelson Felix of IBM stepped in as a last-minute substitute speaker for Heike Riel, who had travel problems.  He did an impressive job.  The first half of the talk was an overview of traditional computer performance scaling and I noticed one graph crowded among others that showed the cost per transistor reached a minimum at the 28 nm node.  I’ve seen this type of plot before, but not from a chipmaker.  This section ended with an incredible quote:  “Process control is the new scaling.”  The second half of the talk was devoted to IBM’s progress in Quantum Computing and it was impressive.  With their superconducting (Josephson Junction) qubit approach they have integrated more that 1000 qubits onto a chip.  To be clear, these are physical qubits, not logical qubits.  The number of logic qubits is the “N” that goes into the 2^N equation that everyone shows to explain the incredible potential of quantum computing.  But due to a very short decoherence time many redundant qubits are required for error correction, and the ratio of physical qubits to logical qubits is very high (up to 1000).  Pushing this ratio down is extremely important to the success of quantum computing and the reason that quantum computer development is not just a scaling game of increasing physical qubits.  IBM’s claim is that qubit stability is also improving and the number of logical qubits available (a number never mentioned) has reached the point where quantum computers can now rival classical computers for some real-world problems.  This “quantum supremacy” point has been claimed many times by many companies in press releases over the last few years, and I never believe them.  It looks like IBM may be close.

Updates on the readiness of negative tone metal oxide resists for EUV exposure showed nice progress.  Lam’s dry resist continues to improve its stochastics, as seen in talks by Zhengtio Chen of Lam and Indira Seshadri of IBM.  Both supplemented traditional LER/LWR measurements with electrical defectivity using meander and fork patterns to detect line/space bridges and breaks with defectivities as low as one per meter line length.  In the patterning materials conference Samsung used a metal oxide resist with a brightfield mask to print contact holes with reduced dose and low local CD uniformity (LCDU, though Samsung calls it IPU, CD “in-point uniformity”).

An aside:  it seems that SPIE has given up on its “No Photography” policy during talks and instead relaxed it to no video recordings.  I suppose this is reasonable since the no photography rule was uniformly ignored.  As I jumped from the optical and EUV conference to the materials conference and sat in the back of the room, the implications of this change were evident.  At every slide change by the speaker, one hundred cameras rose up in unison around the room to take pictures of the new slide, as if choreographed.  It is now allowed, but it is still distracting.

The afternoon brought me back home to the metrology conference.  Gian Lorusso showed very interesting results on the use of a high-voltage (15 kV) CD-SEM to improve the resolution for high-NA EUV printed patterns.  (Full discloser – I am a coauthor on that paper.)  The typical 500 V imaging is running out of steam, since the interaction volume of the electrons within the resist is large enough that when the beam strikes one edge of a < 10 nm wide feature, some electrons escape out of the other edge.  This correlates the roughness of the two edges, making LWR measurement impossible.  A higher voltage not only increases the resolution of the SEM, it reduces the left-right edge correlation of small features and makes LWR measurement possible again.  The worry, of course, is sample damage (and especially resist shrinkage).  After all, we have been regularly reducing voltage to reduce shrinkage.  Lorusso’s thesis is that lower voltage is better up to a few kV, but that even higher voltages might in fact reduce sample damage (at least in the top layer) by having electrons deposit more of their energy deeper into the substrate.  His preliminary shrinkage data bore this theory out, and I suspect we will here more about high-voltage measurement of small patterns in the future.

I gave a talk with imec on the stochastic failure of vias to make electrical contact with metal line-ends.  Using a modeling approach that Mike Adel and I developed over the last few years (and recently published in JM3), measurement of via stochastic variations coupled with line-end tip-to-tip variations were used to predict variations in overlap area between the hole and the line-end.  Given a minimum required area of overlap, these measured stochastic variations can be translated to failure rates as a function of overlay error between the two layers.  What is the minimum area of overlap required for a good electric connection?  That number was determined by comparing the model results to voltage contrast measurements.  The fit of the model to the data was excellent, if I do say so myself.

Alas, my afternoon was taken up with customer meetings.  I love meeting with my customers, but don’t like missing so many good talks.

My day came to a very satisfying end at the KLA party celebrating 40 years of PROLITH.  As I mentioned earlier, I gave my first-ever conference talk at this conference in 1985 and introduced PROLITH to the world.  At the end of that talk I mentioned that I would send the software (free) to anyone who gave me their business card.  I got 80 cards.  Using the language that I now understand, I would call that an indicator of market demand.  Five years later I started FINLE Technologies to commercialize PROLITH.  After adding some great people to the team, like Ed Charrier and Mark Smith, we sold FINLE to KLA in 2000.  I left KLA in 2005, and I am proud to say that I don’t think they even missed me.  Today PROLITH is doing amazingly well, providing the most rigorous full-chip simulations available – a truly amazing accomplishment.  Looking at that timeline, you can see that PROLITH has been outside of my tutelage for just as long as it was under it.  Congratulations to the PROLITH team, and good luck for the next 40 years!