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Isle of Rhodes, Greece , September 23-26, 2019
I have a confession to make.
Sometimes I choose to go to a conference mostly based on its
location. My core
conference is SPIE’s Advanced Lithography, and I would go to that
wherever it was (San Jose is nice, but it is not a “destination”).
But there are a number of conferences at the periphery of
lithography, and in particular conferences that touch on lithography
for the academic community.
Three conferences that fit this bill are the Electron, Ion,
and Photon Beam Technology and Nanofabrication conference (EIPBN,
often called 3-beams or triple beam) in the US, Microprocesses and
Nanotechnology Conference (MNC) in Asia, and Micro and Nano
Engineering (MNE) in Europe (thought of as sister conferences).
They can be interesting, informative, thought provoking, and
even inspiring. But
often there is little of direct relevance to my current focus.
In other words, I don’t need to go, but sometimes I want to
go. How much I want to
go depends on where it is.
This year, the MNE conference was on the island
of Rhodes, Greece, and guess what?
I wanted to go.
These three conferences, EIPBN, MNC, and MNE,
used to have a lot more lithography content, much of which was
relevant to semiconductor lithography.
Today, however, semiconductor lithography has priced itself
out of the academic market, and universities employee either vastly
outdated lithographies, or high-resolution approaches that are so
slow they could never be considered for the semiconductor industry.
Still, it is always nice to find out what the academic
research community is up to in the world of lithography.
But frankly, for me, it is generally not worth
traveling half-way around to world to go to one of these
conferences. Unless I
want to.
And so I found myself this week in Rhodes,
Greece, listening to interesting papers, presenting one myself, and
enjoying the amazing beauty and heritage of the one of the Greek
islands.
The MNE conference is extremely vibrant, with a
lot packed into three days:
150 orals, 360 posters, and four evenings of social
activities. Student
participation is huge (often the point of an academic conference),
and as an old, cynical industry guy, it is refreshing to be around
enthusiastic young people.
The plenary session started with an old friend
– Yan Borodovsky, retired from Intel, who talked about Moore’s Law:
Past, Present, and Future.
As he told me after, “I can’t believe I am still being asked
to speak when in my 5th year of retirement!”
For a retired guy, he gave a great talk.
His “past” described the three pillars of microelectronics:
Von Neumann’s computer architecture of CPU, memory, and I/O,
Moore’s Law of reducing transistor costs, and Dennard scaling that
makes a transistor better when it is smaller.
One by one these pillars of microelectronics are falling
away. Dennard scaling
ended in the mid-2000s when voltage scaling became increasingly
difficult. Smaller
transistors are no longer better, we just hope they are not terribly
worse. Moore’s Law has
dramatically slowed of late, and Yan made a bold prediction – the
end of reduced cost per transistor would occur in 2021, coinciding
with the attempt to bring EUV lithography into high volume (really
high volume) manufacturing.
The last pillar, Von Neumann’s architecture, is the hardest
to escape given its phenomenal success.
But current high-performance computing is limited both by the
speed and power consumption associated with transferring data back
and forth from memory to CPU.
New architectures, such as neuromorphic computing, could
redefine these limits.
Yan’s main point was that lithography choices
have always been based on the constraints of these three pillars.
He added one further important constraint:
that today’s logic chips (such as CPUs, GPUs, and Application
Processors) are seriously defect intolerant.
One defect (for example, one missing contact hole) will kill
an entire chip. This
reality rules out any lithography approach with defect densities
greater than about 0.1 defect/cm^2.
That’s a shame, since lithographies such as directed
self-assembly (DSA) and nanoimprint lithography (NIL) are high
resolution and cheap, but don’t have the defect densities required
for today’s logic devices.
A change to a computing architecture that is fundamentally
defect tolerant would enable lower-cost lithography choices.
Since today’s chips have 50% or more of their cost coming
from lithography, the impact would be huge.
It was clear that Yan is hoping for a defect-tolerant future,
so that lower-cost lithography approaches become practical.
As am I.
There were only a few other talks specifically
relevant to semiconductor folks like me.
B.T. Chan of imec talked about the etch challenges that come
with making FinFETs with only one or two fins.
Michal Danek of Lam Research talked about atomic layer
deposition and atomic layer etching as enablers to 3D NAND devices.
The social interactions of the conference were
some of the highlights for me.
The reception Monday night before the start of the conference
brought us to crusader-era architecture (the Knights of Saint John
ruled the island from about 1300 to about 1500) in the old town of
Rodos (Rhodes). It was
lovely, and included Homeric singing (what a treat).
Tuesday night was a beach party (we could see Turkey from the
beach). Wednesday night
was the conference reception, and I had the honor of serving as a
judge for the very popular Micrograph contest.
John Randall began the micrograph competition at the 3-beams
conference in 1995, and he brought it to MNE in 2005.
This year there were over 60 entries, and the judging was
hard. You can find this
year’s micrographs at
https://www.zyvexlabs.com/contests/2019-3/.
The conference ended Thursday night with a bus
trip to Lindos, an ancient and beautiful city.
A fitting end to a conference defined, for me, by its
location.
Chris Mack is a writer and lithographer in Austin, Texas.
© Copyright 2019, Chris Mack.
� Diaries from other lithography conferences...