Moore’s Law has always been about economics: if we follow the trend of Moore’s Law, we can reduce the cost per function for our integrated circuits, making chips more powerful for the same cost, or making chips of a given capability cheaper. Historically, cost per function has decreased by about 29% per year, corresponding to a factor of 2 decrease in cost every two years. There are signs that this historic cost reduction trend will slow down. How much of a slowdown can our industry tolerate? If the cost per function is expected to decrease by less than 10% per year going forward, it is unlikely that chipmakers will be willing to invest the massive amounts required for a new generation of fabs. I suspect that the minimum cost per function decrease we can live with is about 15% per year.

What does this say about lithography costs and capabilities per technology node? The cost/function of a chip is the ratio of the cost/area of finished silicon from making the chip and the functions/area that the technology node can deliver. Over the last decade we have been on a 2-year technology shrink schedule, so that the functions/area double every two years. Thus, by keeping the cost/area constant, we have been able to reduce cost/function by 29% per year. If we stay on the same 2-year shrink cycle, a minimum allowed 15% cost/function decrease per year would allow a maximum of 20% increase in the cost/area of silicon each year. Alternately, if we keep the cost/area of silicon constant, we could slow down the 2-year technology node shrink cycle to 4 years between technology nodes, and still get the required 15% reduction in cost/function per year.

Of course, everyone in the semiconductor industry would love to stay on our historic trends: constant cost/area of finished silicon, and a two year cycle of doubling the functions/area. It seems unlikely that this trend can be maintained during the current decade, however. Thus, using a minimum allowed cost/function decrease of 15%/year as a target, we can either allow chipmaking costs/area to increase by 20% each year and stay on the 2-year technology node cycle, or we can allow our technology node cycle to slow to every four years while keeping manufacturing costs/area constant. Either option will allow for continued success, and probably a bit of growth, for the semiconductor industry. But if the technology shrinks come too slowly, or costs rise too quickly, the days of Moore’s Law will be numbered.

As expected, the first EUV session of the last day of the conference filled a large room. It was time to hear the status of EUV tool development, in particular the EUV sources. ASML started things off with a rosy recounting of the successes of 2011. After installing their sixth NXE:3100 preproduction tool, ASML bragged of the 5300 EUV wafers processed at customer sites by these six tools in 2011. I couldn’t help remembering the ASML press release from last month saying a single 193i tool processed 4000 wafers in a day. That, in a nutshell, is the gap between preproduction and high volume manufacturing. They have a long way to go.

The EUV source status reports made future progress to higher power sound inevitable. Today, customers have sources with 9W of power at the intermediate focal plane, a 20W upgrade is being qualified, 50W has been demonstrated, and getting to 100W by the end of the year is straightforward. What could be easier? Somehow, I remain skeptical. Maybe it is because neither source presentation mentioned the damage caused by tin debris – the 5kV shorts or the frequent replacements of $1M collector mirrors – which can only get worse as source power goes up. Maybe it is because the roadmaps made the optimistic assumption that doubling the input laser power would double the EUV source output. Maybe it is because every past source milestone has been missed and it seems likely that future progress will be harder than past progress. Maybe it is because nature does not like EUV.

Or maybe I am biased. I wish the source vendors luck in reaching their goals. They are under a lot of pressure. In contrast, there was frequent mention of significant progress in EUV photoresists. A demonstration of 16 nm lines and spaces looked promising, though the dose was 33 mJ/cm2 (most people are hoping for 20 mJ/cm2 eventually) and the LWR was 3.7 nm, 23% of the nominal CD. This is progress certainly, but I find it very hard to believe that both dose and LWR will be appreciably reduced by next year.

I enjoyed the session on roll-to-roll printing, especially the Rolith presentation on a cylindrical phase-shifting mask with a UV lamp inside. This world of super-high volume patterning on continuous rolls of low-cost substrates is so different from what I think of as lithography that I could do nothing but look on in amazement.

The day ended for me with the last optical lithography session, where Nikon and ASML presented the current status of the latest 193-nm scanners. While single-patterning resolution remains fixed, the rest of the tool is getting better: CD uniformity, overlay and throughput. Under ideal conditions, CD uniformity can be less than 1 nm, single machine overlay can be less than 2 nm, and throughput can be over 220 wafers per hour (with a roadmap to >270 wph). These tools are becoming optimized for double patterning.

My favorite quote of the day: “Math works.” – John Biafore, commenting on a presentation showing a successful simulation prediction.

My least favorite quote: Cymer, talking about their improved internal EUV source testing facilities, said they will “hopefully learn faster than [the chip companies] do.”

And so another SPIE Advanced Lithography symposium is over. Till next year.

I continue to focus on line-edge roughness in my own research. This means that I attended papers in every conference in the symposium, since LER is an issue that cuts across all topics in lithography. (To be truthful, I meant to go to a paper in the new etch conference that talked about LER, but never made it.) LER is finally, in my opinion, getting the attention it deserves. I believe, and say to anyone who will listen, that LER is the ultimate limiter of resolution in optical lithography (e-beam as well). In fact, that was the title of my talk on Wednesday. I think that LER is a core component of Tennant’s Law, that it is killing EUV (in the same way that EUV source power is killing EUV), and that it will limit how far 193-nm lithography can be pushed. And the many difficulties of LER is one reason that directed self-assembly (DSA) so attractive.

Wednesday began for me with another tour-de-force paper by Chris Bencher and coauthors (Applied Materials and IBM) on continued progress on defectivity for DSA. Their work showed that defect inspection and review tools were capable of enabling progress for DSA, and that defect levels, while not zero, are low enough to do serious work on finding and eliminating the defects that are there. This is good news. Many people are scared that DSA defects are somehow thermodynamically inevitable, or that the statistics of DSA defectivity scale in some ugly way. That doesn’t look to be the case. Among other things, Bencher inspected 550 million contact holes on a DSA wafer and found 22 were missing (one of the fears of DSA, as well as for most lithography schemes, is missing contacts). This is a rate that makes finding defects hard, but getting to sufficiently low defect rates probable.

The next step is to get semiconductor-grade block-copolymer materials into the fabs for testing on real processes. And that is starting to happen. Yuriko Seino of Toshiba showed some amazing results of a DSA contact hole shrink process that looked almost ready to be used in manufacturing. Contact holes were printed in a guide material of spin-on carbon (CD = 72 +/- 8 nm, LER = 3.9 nm) on 300-mm wafers. A PMMA-Polystyrene block copolymer was spun on, filling the holes with the self-assemblying polymer (a ring of polystyrene forms along the outside of the contact, with PMMA in the middle). A DUV flood exposure made the PMMA soluble in an organic developer. After development, the DSA holes had a CD of 28.5 +/- 1.4 nm, with an LER (or CER, contact edge roughness) of 0.7 nm. Amazing results – but this is what DSA does. Still to come are electrical via chain yield tests – an essential test of the overall process capability.

An interesting problem that must be tackled before DSA can be used in manufacturing is the impact of this process on design. In the contact hole shrink process (the most likely place DSA will first appear in manufacturing fabs), arbitrary contact holes on arbitrary grids are not possible. Instead, DSA will assembly to produce a specific contact hole size, and will be in the right spot only if those holes are on a proper grid. Both of these issues will significantly impact chip layout. Which is why I was excited to see a paper from Stanford on DSA-aware layout for random logic. With the right design approach, the limited range of contact hole features that can be printed with DSA can be a big advantage.

Unfortunately, on Wednesday I had to reprise my role as self-appointed ethics policeman for papers. A company (that should have known better) gave a paper presenting a new model they had developed. They kept all aspects of how the model worked secret, revealing not even the least detail (for competitive reasons, no doubt). Further, the model was not commercially available – it was for internal use only. As a result, after listening for 20 minutes I could come away from that talk with absolutely nothing. The minimum (and foundational) ethical principle of scientific publication is that sufficient detail be given so that others can reproduce the work. Otherwise, the paper is not a scientific one – it cannot be used to build our shared body of knowledge. I used the question period at the end of the presentation to explain this basic principle to the author.

After another poster session and several beers at KLA-Tencor’s PROLITH party, the third day of Advanced Lithography came to an end. Tomorrow morning will bring the EUV tool and source status review papers. I predict a full house at that session.

There is no place I’d rather be on Valentine’s Day than in San Jose surrounded by my friends and colleagues in lithography. No wait, I didn’t mean that. I miss my wife and two young daughters. I don’t like traveling without them.

While Valentine’s Day is the Hallmark holiday I despise the most, it does serve to remind me of the conflicted feelings of most business travelers who have families. Over the years I have missed holidays and birthdays and uncountable little things in the lives of the people I love most. I have also been to interesting and exotic places, met great people (many of whom have become lifelong friends), and worked on fun and intellectually satisfying projects. Mostly, I’ve been able to keep these things in balance during the various phases of my life, and for that I am grateful. While popular culture celebrates those who live their lives in the extreme, the wise know that happiness and success is about balance.

But there is no balance this week. This week is non-stop, metal to the floor, take no prisoners lithography. Tuesday began with papers at 8am and the last panel ended at 9pm, with for me a lunch meeting and poster session in lieu of dinner thrown in as well. I ran constantly from session to session (trying not miss the most interesting papers), and constantly ran into colleagues I see only once each year (trying to remember their names while not looking down at their badges). I ended the day with a shot of Jameson’s at Original Joe’s, tired but satisfied.

I also had two papers, one oral and one poster. Luckily, I had them both prepared well in advance. (People that know me are laughing out loud right now.) In truth, the stress and adrenaline of just-in-time presenting makes this conference even more exciting, though I swear every year that this year will be the last time I am so disorganized. Now if only I could finish my talk for tomorrow…

I saw many interesting papers of the solid, incremental advancement type – the lifeblood of this conference. I criticized a few of them, mostly for failing to learn the lessons I’ve already learned and repeating the mistakes other authors have already made. Nobody can read and absorb the entire literature and history of an industry, which is why the format of conference presentation is so valuable. The communication and teaching is two-way. You tell the audience what you have done and learned in the hopes of teaching them, and they give you feedback as to how that fits within the community’s vast knowledge base. The bigger and more diverse the audience, the better. But make no mistake, baring your technical soul for inspection is a scary thing, especially for the many young folks presenting here for the first time. I congratulate each author for their mettle – success is in the doing.

My sense of the mood at the conference is one of disappointment with the progress of EUV lithography. Roadmaps are slipping because of source power. Progress in line-edge roughness reduction is almost nonexistent. The major ASML papers on EUV progress are yet to come.

While everyone is excited about directed self-assembly (there are 55 DSA talks this year, compared to 20 last year), there are still many unknowns. I suspect, however, that a first application of DSA is emerging that could jumpstart its transition from lab to fab: contact hole shrinking. After exposing the contact holes to be bigger than we want them, DSA polymers coat the inside of the hole, both shrinking them and healing most of their roughness. A neat trick. While this approach does nothing to improve contact hole pitch, it looks like an important and valuable tool for printing one of the most difficult lithography layers.

My favorite quote of the day: “What does not change in lithography is change.” – Tatsuhiko Higashiki, Toshiba. My favorite new acronym: InStED Lithography (Interference Stimulated Emission Deactivation Lithography) – John Petersen.

Attendance at this year’s Advanced Lithography Symposium is up 10% this year, to over 1500, though we still haven’t recovered from the huge drop in numbers that accompanied the economic collapse in 2008. Still, the mood here is good. When I ask people how they are doing the answer is almost universally the same: busy. And busy is what we will all be this week, trying to navigate the seven conferences (six in parallel), 12 short courses, three panel discussions, multiple company-sponsored technical forums and hospitality suites, and of course the numerous side meetings, customer dinners, and hallway encounters that give AL its social dimension and where much of the real work of information transfer occurs.

For me the conference started out with my short course (informally titled “The World According to NILS”). The students were especially enthusiastic, which always gives me a great energy boost to start the week. But if I hadn’t been teaching, I’m sure I would have been attending the new short course on directed self-assembly (DSA). It was by far the most popular course this year.

On Monday the conference began with the Plenary Session. John Bruning won the Frits Zernike Award for Microlithography, though he wisely chose not to change his vacation plans in the Caribbean with his wife in order to accept the award. Burn Lin was recognized for his ten years of service as the founding editor-in-chief of the Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3). Since I have taken over from Burn as the new editor-in-chief, the well-deserved praise and recognition that he received only made it more obvious how big the shoes are that I must fill. We also welcomed four new SPIE fellows into our ranks: Patrick Naulleau, Andy Neureuther, Vivek Singh, and Yu-Cheng Lin. Congratulations to all of them.

The three plenary talks were all very good. Jim Clifford, operations VP at Qualcomm, made sure we all understood how much our children (and grandchildren) would be addicted to wireless devices, and how they needed continuation of Moore’s Law to make that happen. His message was “If you build it, we will come.” But with a caveat. The first slide of his talk had only one word: COST. Lest we think that Moore’s Law meant anything different, he assured us that it means lowering the cost per function over time. A more powerful chip that doesn’t have lower cost per function is simply not interesting to Qualcomm. How much lower? I asked that question and got a straight answer. Historically, our industry has achieved 29% reduction in transistor cost each year. Clifford thought that cost reduction below the “low double digits” would not be worth the investment. So, Moore’s Law can slow somewhat, maybe even by a factor of two, but if it slows any more than that it will be dead. Clifford ended the talk by encouraging us lithographers to work hard: “I want to tell you how important you are to my retirement.”

Grant Willson had a great plenary talk full of poetry and insight. Chris Progler of Photronics kept us informed and entertained as he inundated us with data and conclusively proved that squares don’t make good Frisbees.

The crowds are always the biggest on the first day, since people have yet to burn out from technical information overload. I had to watch the first EUV papers in the overflow room. There I learned about ASML’s progress on getting the throughput up on the NXE:3100 preproduction EUV tool. Last year, shortly after installing the first 3100 at Samsung, ASML announced that the throughput would be a disappointing 5-6 wafers per hour (the spec was 60). One year later, ASML showed that the actual throughput was now 4 wafers per hour. Not exactly the progress we had been hoping for. Why the backslide? The quoted “6 wph” was based on a mythical “10 mJ resist” (the throughput numbers for the NXE:3300 will be based on a 15 mJ resist). Such a resist does not (and I’m sure will not) exist. The actual 4 wph was based on a “usable dose”, though the results did not produce acceptable linewidth roughness (LWR), so there is some doubt on just how usable that dose really is.

Burn Lin also had a standing room only overflow crowd for his talk on multiple-electron-beam lithography (we are very interested in both EUV and alternates to EUV). He made the REBL group at KLA-Tencor very happy with the bold proposal that we should make every layer on 450-mm wafer devices using e-beam lithography, and in particular with REBL (reflective electron-beam lithography). His analysis was good, but made some very important assumptions: REBL will perform to specification, be delivered on-time, and at the currently estimated price. If that happens it will be a first for an NGL technology.

I heard some good talks by Moshe Preil and Jim Thackeray, some poor talks by a few others, and the week of technical papers has begun. Now if I can only finish my talk in time to give it tomorrow…

Monday is always the most quotable day of the symposium. Here are some of my favorites:

“EUV is like a trip to Disneyland.” – Jim Clifford
“I’ll retire when I expire.” – Grant Willson
“EUVL is needed in 2004 or sooner.” – Peter Silverman of Intel, in a talk from 2000 (as quoted by Grant Willson)
“Nothing fails this year’s technology faster than aiming for last year’s targets.” – Moshe Preil

Yesterday I found my way to San Jose (a more arduous journey than in the past, since all direct flights from Austin to San Jose have disappeared like civility in American politics). Another SPIE Advanced Lithography Conference is about to begin. As usual, I will blog each day from my vantage as an overwhelmed conference participant. And also as usual, I will set the stage for what I think will be the highlights of the week in this prologue. I hope, of course, that I am wrong – that will mean that I don’t know what will be important and a surprise is in store. Surprises are the best thing about this conference. And I have never been bored here yet.

Let’s begin with the obvious topic: EUV lithography. I believe that 2012 will be the make or break year for EUVL. I’ve said that before. In 2010 and 2011, in fact. I continue to be amazed at how willing customers are to live with missed specs and slipped deadlines. I guess that’s what happens when you have no alternatives. But this time I mean it: 2012 is the make or break year for EUV. And of course, all eyes are on ASML and their source suppliers.

Last year ASML shipped 6 NXE:3100 “pre-production” EUV tools (actually, the first one was in 2010), at an estimated $120M each. While spec’ed at 60 wafers per hour throughput, they delivered 6 wph. An upgrade of the source by Cymer to bring that close to 20 wph has been delayed. Meanwhile, the production tool NXE:3300 is supposedly still on schedule for delivery in the second half of this year. But wait: the spec on throughput for the 3300 has changed. It is now 69 wph, down from an original 125 wph, which is down from even higher expectations. The higher 125 number will come later, we are told, with an upgrade to the source. It’s all about managing expectations. And twisting arms. Did I mention there are no alternatives?

But expectations are not the only thing that matters. Eventually, real throughput on real product will matter. Which brings up an interesting question – one that I hope to gain more insight on this week. How high does “high” have to be in High Volume Manufacturing (HVM)? What’s the lowest actual production throughput that customers can live with and still think EUV was worth the commitment? The fabs aren’t talking. Understandably, they don’t want to give ASML the lowest number, since that will take the pressure off them to do better. And different customers will have very different answers, I’m sure. Will Intel buy 10 EUV tools if those tools can only deliver 40 wph in production?

A related but more technical question is also on my mind: How much line-edge roughness (LER) can devices tolerate at the 14-nm node and below? This question is related to throughput because the easy way (and maybe the only way) to reduce LER is to increase exposure dose. And in source-limited technologies like EUV and electron-beam lithography, throughput is mostly determined by the resist dose requirement. (See my previous posts on Tennant’s Law.) So, as always, I’ll be focusing on the LER papers this week, hoping to gain enough insight to say I actually understand LER, what causes it, and how small it can be made.

As I’ve said before, LER is the ultimate limiter of resolution. Unless, that is, we break the LER paradigm of our current exposure and resist approaches. One way to do that is with directed self-assembly (DSA). This year’s hot topic will, no doubt, be DSA. The technology has shown enough promise that it has gotten the industry excited, and there has been a lot of activity in the last year. Soon, however, and maybe this week, reality will set in. Getting DSA to work in production will take an enormous effort.

I’ve seen these cycles before: A promising new idea gets people excited. There is potential to solve a nagging industry problem, or enable a future generation of products. After the early adopters report on their progress (and those reports are always glowing), the early followers jump in and start working out the details. Then they come to this conference and start reporting on the problems they are having. Solutions to those problems are proposed and people get back to work. But do the solutions come fast enough, or does the excitement wane? If the problems pile up too fast, people looking for a quick fix give up. A few diehards labor on. Progress is slow, coupled with complaints that EUV is getting all the resources. Will the new idea survive these travails, eventually become a “plan of record” at enough fabs to be self-supporting? The answer will depend on the difficulty of the problem and the grit and wits of the diehards.

Does this sound familiar? It could describe sidewall-spacer double patterning (made it), or litho-freeze-litho-freeze double patterning (hasn’t made it), or model-based OPC (made it), or imprint (hasn’t made it). And it will describe DSA, though we are a few years away from knowing the outcome.

What else will I be watching for this week? Ah yes, the surprises. Hopefully, I won’t be in the wrong session when they occur.

In the first part of this article, I talked about the empirically determined Tennant’s Law: the areal throughput (At) of a direct-write lithography system is proportional to the resolution (R) to the fifth power. In mathematical terms,

At = kT*R^5

where kT is Tennant’s constant, and was equal to about 4.3 nm-3 s-1 in 1995 according to the data Don Tennant collected [1]. The power of 5 comes from two sources: (1) areal throughput is equal to the pixel throughput times R^2, and (2) pixel throughput is proportional to the volume of a voxel (a three-dimensional pixel), R^3. The first part is a simple geometrical consideration: for a given time required to write one pixel, doubling the number of pixels doubles the write time. It’s the second part that fascinates me: the time to write a voxel is inversely proportional to the volume of the voxel. It takes care to write something small, and it’s hard to be careful and fast at the same time.

The implication for direct write is clear: the economics of writing small features is very bad. Granted, Tennant’s constant increases over time as our technology improves, but it has never increased nearly fast enough for high resolution direct-write lithography to make up for the R^5 deficit.

But does Tennant’s Law apply to optical lithography? Yes, and no. Unlike direct-write lithography, in optical lithography we write a massive number of pixels at once: parallel processing versus serial processing. That makes Tennant’s constant very large (and that’s a good thing), but is the scaling any different?

For a given level of technology, the number of pixels that can fit into an optical field of a projection lens is roughly constant. Thus, a lower-resolution lens with a large field size can be just as difficult to make as a higher-resolution lens with a small field size if the number of pixels in the lens field is the same. That would give an R^2 dependence to the areal throughput, just like for direct write (though, again, Tennant’s constant will be much larger for projection printing).

But is there a further R^3 dependence to printing small pixels for optical projection printing, just as in electron-beam and other direct-write technologies? Historically, the answer has been no. Thanks to significant effort by lithography tool companies (and considerable financial incentives as well), the highest resolution tools also tend to have the fastest stages, wafer handling, and alignment systems. And historically, light sources have been bright, so that resist sensitivity (especially for chemically amplified resists) has not been a fundamental limit to throughput.

But all that is changing as the lithography community looks to Extreme UV (EUV) lithography. EUV lithography has the highest resolution, but it is slow. Painfully slow, in fact. Our EUV sources are not bright, so resist sensitivity limits throughput. And resist sensitivity for EUV, as it turns out, is a function of resolution.

For some time now, researchers in the world of EUV lithography have been talking about the “RLS trade-off”: the unfortunate constraint that it is hard to get simultaneously high resolution (R), low line-edge roughness (L), and good resist sensitivity (S, the dose required to properly expose the resist). Based on scaling arguments and empirical evidence, Tom Wallow and coworkers have found that, for a given level of resist technology [2],

R^3 L^2 S = constant

Since throughput is limited by the available intensity from the EUV source, we find that, for a fixed amount of LER,

Throughput ~ 1/S ~ R^3

Finally, since the number of pixels in a lens field is fixed, the areal throughput will be

At ~ (lens field size) R^3 ~ R^5

Thus, like direct-write lithographies, EUV lithography obeys Tennant’s law. This is bad news. This means that EUV will suffer from same disastrous economics as direct-write lithography: shrinking the feature size by a factor of 2 produces a factor of 32 lower throughput.

Ah, but the comparison is not quite fair. For projection lithography, Tennant’s constant is not only large, it increases rapidly over time. Tim Brunner first noted this in what I call Brunner’s Corollary [3]: over time, optical lithography tends to increase Tennant’s constant at a rate that more than makes up for the R^2 dependence of the lens field size. As a result, optical lithography actually increases areal throughput while simultaneously improving resolution for each new generation of technology. Roughly, it seems that Tennant’s constant has been inversely proportional to about R^2.5 as R shrank with each technology node.

But that was before EUV, and before the R^3 dependence of the RLS trade-off kicked in. At best, we might hope for an effective Tennant’s law over time that sees throughput go as R^2. This is still very bad. This means that for every technology node (when feature sizes shrink by 70%) we’ll need our source power to double just to keep the throughput constant. The only way out of this dilemma is to break the RLS “triangle of death” so that resolution can improve without more dose and worse LER.

Is the RLS trade-off breakable? Can LER be lowered without using more dose? This is a topic receiving considerable attention and research effort today. We’ll have to stay tuned over the next few years to find out. But for all the risks involved with EUV lithography for semiconductor manufacturing , we can add one more: Tennant’s law.

[1] Donald M. Tennant, Chapter 4, “Limits of Conventional Lithography”, in Nanotechnology, Gregory Timp Ed., Springer (1999) p. 164.
[2] Thomas Wallow, et al., “Evaluation of EUV resist materials for use at the 32 nm half-pitch node”, Proc. SPIE 6921, 69211F (2008).
[3] T. A. Brunner, “Why optical lithography will live forever”, JVST B 21(6), p. 2632 (2003).