“It is possible to get an education at a university. It has been done; not often.”
– Lincoln Steffens, 1866-1936
All posts by Chris
Steven A. Orszag, 1943 – 2011
Dr. Steven A. Orszag, a renowned expert in computational fluid mechanics, died on May 1 at the age of 68. (His obituary in the New York Times can be accessed here.) One of his most important contributions was the development of spectral methods for solving complex fluid dynamics problems, greatly increasing the efficiency of the numerical calculations. These techniques are now standard in fluid dynamics, especially for turbulent flow, but are also used in a number of other applications of scientific computation.
It is one of those other topics that caused me to meet Steven. Dr. Orszag had a long collaboration with Dr. Eytan Barouch, of Clarkson and then Boston Universities. Eytan got involved in lithography simulation in the late 1980s (I worked with him quite a bit during those early years) and applied Orszag’s spectral methods to aerial image simulation problems. Eventually Barouch and Orszag formed Vector Technologies to market their lithography simulator FAIM. Orszag’s involvement was mostly advisory and on the technical side, so far as I could tell. In the 1990s Dr. Orszag was the coauthor of 16 SPIE proceedings papers on lithography simulation, and I met him a time or two at these conferences. Obviously bright and busy, it was clear to me that lithography was more of a hobby to Dr. Orszag, an interesting offshoot of his many scientific interests.
Steven Orszag also has a famous son – Peter Orszag, formerly the budget director for the Obama administration.
Celebrating Long Life
Yesterday I learned that my neighbor, Carroll McPherson, died. He was 101 and a half. When you are very young and very old, you get to count by half years. He died in his bed, surrounded by his family, in the home he has lived in since 1942. He was ready to die, at peace and waiting for death for the last year or so, though his body clung to the habit of life. I want to be like Carroll.
I’m sorry that I was not there to say the last goodbye, and to help his wife Martha and the rest of his family like our other neighbors did. I’m visiting my wife’s grandfather Ben in Washington to celebrate his 90th birthday. Like Carroll, Ben has lived a healthy and happy life, and just seems to keep on going. I want to be like Ben.
Tomorrow is the big birthday party, and when we are done toasting Ben, I’ll give a small toast to Carroll as well. The cycle of life can be beautiful even in death.
Quote of the Day
“Welcome to the fact-free zone.”
– Gail Collins, describing the current Texas legislative session in Austin. To read her full editorial in the New York Times, click here.
Still Room at the Bottom
Fifty years ago today, Russian cosmonaut Yuri Gagarin became the first human to leave Earth and enter space. (He was perfectly qualified for the job: he was short, and was willing to sit there and do nothing as he was hurled like a cannon ball into space.) If sputnik awoke the world to the technical possibilities of space, Gagarin awoke our sense of awe and adventure for space. I grew up in the sixties thinking that almost anything was possible, and that our future would be filled with bigger and better things. Flying into space implied that no barrier was too high to be surmounted by human ingenuity and effort.
But fifty years later the promise of space travel remains mostly promise. When I watched the 1968 film 2001: A Space Odyssey in 2001 (didn’t we all), I was struck by how little of our early vision for space exploration had actually come about. There is a simple lesson here that is very easy to forget: scaling up is hard. To build a building twice as tall requires more than twice as much steel and concrete. Launching twice the payload into space requires more than twice the rocket power. The scaling is superlinear, and that doesn’t make for good economics (or good physics). In our gravity-constrained world, bigger is sometimes better, but it is always much, much harder.
At the same time that most of us earthlings were swooning over the first manned space flight, a handful of engineers at Fairchild Semiconductor were working out the kinks on a much smaller project – connecting four transistors together on one slab of silicon to make the first commercial integrated circuit. Not too many people noticed this innovation at the time, let alone appreciated its significance. There would be no ticker-tape parades (though there would eventually be quite of few millionaires among this talented group, and even a few billionaires). But something important had begun, and the promise of the silicon IC revolution has exceeded all expectations.
(It’s interesting to note that much of the early work on integrated circuits was funded by the Apollo program in its desire to miniaturize electronics destined for space.)
And so another simple lesson is learned: scaling down doesn’t behave like scaling up. Not to say that making something smaller is necessarily easier, but smaller mean less – less material, less energy, less space. The scaling works in our favor. Of course, there are limits, and those limits become something close to insurmountable when the dimensions of the device reach atomic scales. But the room between the macroscopic dimensions of our everyday objects and the microscopic dimensions of the atomic scale is something like 6 or 8 orders of magnitude. As Richard Feynman famously said, there’s plenty of room at the bottom. Semiconductor technology has been steadily mining this room at the bottom, shrinking features from 25 microns to 25 nanometers in the last 50 years.
Is there still room at the bottom? I think so. CMOS transistors may only last for another factor of two of shrinking (or less), but other devices will allow dimensions closer to one or a handful of nanometers. And we have not yet begun to think of all the possible things we can make with a vast toolbox of micro- and nanofabrication technologies. (Alas, the phenomenal success of the CMOS transistor has probably crowded out a wide range of other useful devices.) So while the way we have scaled in the past (think Moore’s law) may not last, there is still plenty of room for innovation at the bottom. I suspect that my young children will one day marvel at the progress in scaling down during their lives, while wondering whatever happened to the promise of space travel.
History File – you can’t make this stuff up
A real ad that ran in the Wall Street Journal in 1954, by Mar Samuel (a vicar of the Syrian Orthodox Church), who personally owned four of the dead sea scrolls (he bought them from a shoe maker and antiquities dealer from Bethlehem named Kando). Thanks to this ad, they were bought by the Hebrew University, through an intermediary; they already owned three scrolls. I have not heard how much they paid.
BTW, the dead sea scrolls were uncovered in various caves between 1948 and 1954 in (then) Jordanian-controlled parts of the West Bank. Their importance were not widely recognized until the mid 1950s, after Edmund Willson published his 1955 book “The Scrolls from the Dead Sea”.
Quote of the Day
I was talking last night to my five-year-old daughter Sarah about the difference between poetry and prose. I asked her to define poetry for me. I thought she would say “words that rhyme” and was wondering if I would have the courage to explain that much of it doesn’t (and was realizing that I didn’t know how to define poetry myself). Instead, this is what she said:
“Poetry is words that don’t make a whole lot of sense.”
You know, I think she got the gist of it. (Granted, most of her poetry experience comes from Dr. Seuss.)
By the way, Google gave me these definitions of poetry:
– literature in metrical form
– language exhibiting conscious attention to patterns
– language used for its aesthetic and evocative qualities
– language characterized by romantic imagery
I’m going with Sarah’s definition.
SPIE Advanced Lithography Symposium 2011 – day 4
This week in San Jose began cold, but warmed up by Thursday to the kind of weather we all expect from California. So too with the conference, and I think Thursday had some of the most interesting, and surprising, presentations.
The day began for me with the much-anticipated presentation by ASML on the NXE:3100 extreme ultraviolet (EUV) “pre-production” lithography scanner. As expected, it was by parts marketing pitch, pep talk, and soothing reassurance that everything is under control. The first of six NXE:3100s shipped to Samsung last year, printing its first wafers in December. The second 3100 is being installed now at Imec in Belgium. The other systems will roll out in about two month intervals. Unfortunately, there was no official word (or data) from the system as running at Samsung, but ASML provided a good overview of the performance of the systems at the ASML factory.
You have to give ASML a lot of credit – they know how to build a good tool. The lens quality, resolution, defectivity, and overlay performance was as good as anyone could expect as this point. The “tool flare” was down to 5%, but be careful – the total flare seen at the wafer is the tool flare plus flare caused by the mask and REMA masking blades. This total flare is chip-layout dependent, and was as high as 12% for a Flash chip example they showed (you had to be very close to the screen to see the small “12” in the legend of the graph, but at least it was there).
The performance of the tool was very good, except for two problems. The linewidth roughness (LWR) of all their images was very bad, though not a single LWR measurement was shown in the presentation. But it was the throughput that everyone was most interested in hearing about, and that number was 5 wafers per hour. Of course, that is not a “production” throughput number, since it assumed a 10 mJ/cm2 resist and didn’t expose any edge fields, but it’s still a benchmark number to compare to. It’s better than I thought it would be, but still a factor of 12 from the tool spec of 60 wafers per hour. ASML sought to reassure the skeptical members of the audience by renaming their roadmap for source power an “upgrade path” instead.
As anyone who has known me for a while already knows, I am a skeptic of the viability of EUV lithography for IC manufacturing. It’s not that EUV can’t work, it’s just that the effort required to make it work doesn’t line up with the timing and cost needs of chip manufacturers. When serious work first started on EUV lithography in the mid 1990s, the target insertion into manufacturing was the 130-nm node. Since then, the target has slipped by at least two years for every three years of effort. Today, Intel talks about inserting EUV into manufacturing at their 10-nm node four years from now. The result: tool development has been shooting at a moving target, which is almost always a recipe for disaster.
The 10-nm node for logic means a 20-nm or 22-nm half-pitch, which puts the k1 factor for the half-pitch below 0.5 on the (newly increased) 0.33 NA production tool. This means off-axis illumination will likely be required, and it will be difficult to extend the tool to the next node. Mask blank and patterned mask defectivity is still an unsolved problem, and thanks to a lack of appropriate mask inspection tools we “don’t know what we don’t know” in terms of how bad the problem is. Cost, of course, is just as critical as performance, and a $100M tool will need at least 100 wafers per hour in production throughput (spec’ed throughput much higher) to be viable. The effort required to get beyond 100 wafers per hour is huge, especially since the exposure dose constraints that LWR will put on the resist are not likely to be overcome. We have no roadmap, let alone on upgrade path, for reducing LWR to 2 nm.
And so the final push is on. It will be an all-out effort by the industry for the next 12 – 24 months to try to make EUV lithography work. But ASML has 10 production EUV tool orders in their hands. How did they manage that, given the uncertainty involved and the fact that the preproduction tool has yet to be evaluated? As one chip maker told me, ASML is very good at “twisting arms”. Another chip maker said they had no choice but to “play the game”. After all, ASML controls the spigot on 193-nm immersion tools. So the orders are in, and the industry is sharing the risk with ASML (probably not a bad thing). If this year at the SPIE Advanced Lithography Symposium was interesting, next year promises to be even more so.
To make it clear, I am a skeptic, but I would be happy if EUV lithography was successful. I’m doing my part by trying to understand the fundamentals of LWR. Regardless of the outcome, the EUV effort is fun science and engineering! I hope we will continue to work on the hard problems of EUV in the cold light of reason.
The most pleasantly surprising aspect of this year’s symposium was the variety and quality of work presented at the Alternate Lithographic Technologies conference. Now that EUV has been separated out as its own conference, the Alternate Lithography conference has been able to flourish with exciting presentations on nanoimprint, directed self-assembly, interferometric lithography, and many other innovations. The University of Wisconsin had a great talk on modeling self-assembly. Virginia Tech surprised me with a novel (and potentially revolutionary) approach to double patterning as a non-linear double exposure. And it is always fun to think about the bizarre behavior of evanescent waves, inspired by a very good talk from the University of Canterbury (Christchurch, New Zealand).
And now I’m going home, where I hope to catch up on the sleep I’ve lost in the last week. Am I getting too old for life in the fast lane of advanced lithography?
SPIE Advanced Lithography Symposium 2011 – day 3
Today I talked more than listened. I had two papers, both on stochastic effects in lithography. In one, I showed a complete model for EUV resist exposure and for predicting stochastic uncertainty in the acid concentration at the end of exposure. The second, looking at quenching effects, is unfortunately a work in progress. There is still much to learn. One important lesson is to get my papers done before I come to the conference.
But since I am on the topic of learning about line-edge roughness (LER), I have been very disappointed with the number and quality of this year’s papers on this topic. I’ve said it before and I’ll repeat it here – it is my opinion that line-edge/linewidth roughness (stochastic effects in general) will be the ultimate limiter to resolution in optical lithography. We are already nearing that point, with many at this conference talking about how great some experimental result is “except for the roughness”. From what I can tell, there has been essentially no progress in improving LER since last year, and insufficient progress in improving our understanding of LER mechanisms.
As for LER metrology, I can’t tell whether the metrology is not good enough, or whether metrology users are just unwilling to do it right. Doesn’t anyone realize that measuring noise is inherently noisy? If I measure LWR to be 5 nm, using a typical 128 measurement sample on one image, the 95% uncertainty just from random error is +/- 12%, that is 5 +/- 0.6 nm. I did not see more than one paper that put error bars or uncertainty estimates for LWR in their presentation. I saw several talks that presented LWR values to two decimal places, or showed materials that exhibited 5% lower LWR, without any discussion of the statistical significance of the numbers. Aren’t we engineers and scientists here? We can do better. Samsung gave an interesting talk showing how their measured LWR varied from 3.1 nm to 5.4 nm on the same sample just based on their measurement recipe. Systematic errors on top of the random errors.
And since I’m riled up, let’s talk about LER post-processing, AKA magic rinse. This is where a rinse or vapor or e-beams or ion beams, usually with some heat, is used to smooth out the roughness of the sidewalls of resist. I’m sorry, but this just won’t work. Low frequency LWR is a linewidth error. A rinse can’t remove linewidth errors from the resist (if it does you have even bigger problems to worry about), so it can only remove the high-frequency roughness that doesn’t really matter any way. It’s like using a rinse to remove my gray hair. It might make me prettier, but it won’t make me a nice guy.
OK, I’m off my soap box.
SPIE Advanced Lithography Symposium 2011 – day 2
I spent much of Tuesday learning about alternate lithography schemes. Toshiba gave an update on their efforts to evaluate nanoimprint lithography for chip manufacturing. The technology is closer to prime-time than I expected. Most of the data for 28 nm half-pitch looked very, very good (CDU of 1.2nm, LWR of 2nm, mix-and-match overlay of 10nm), but of course there is one big problem remaining. Mask defectivity is a factor of 100 too high. Toshiba has given themselves one year to bring defect densities down. I wish them luck.
The technology that has excited me the most this year is directed self-assembly (DSA). Several authors have presented phenomenally good 25-nm pitch line/space patterns. This stuff is cool! There are still many things to learn (and to fix) about the technology, but the potential is so great that there is no doubt the industry will aggressively pursue DSA in the next few years. The progress has been very rapid. My favorite quote is from Chris Bencher: “DSA can not be ignored.”
Many people told me there was a lot of buzz around multi-beam electron beam technology. I didn’t see any of the papers (the curse of parallel sessions), but the technology is generating interest. Not everyone is a believer in EUV.
But many people are believers. The EUV conference this year has the most papers of any conference. The bulb glows brightest just before it burns out. But more on that topic later in the week.