Wednesday was, for me, a busy day since I had two talks to give. The first was the opening keynote talk at the Design for Manufacturability (DFM) conference entitled “The future of lithography and its impact on design”. The take-home message was that lithography would become less critical to the success of the industry, and that materials, device architecture, and design would be the key technologies of the future. You can find the presentation here. Afterwards I was surprised when a few people told me they found my presentation depressing or that they were now polishing up their resumes and thinking about a future career in design.

I saw a few updates on Mapper technology, that massively parallel e-beam technique that, if it works, could provide an important solution for complimentary lithography, especially in the foundry business. Unfortunately, their first pre-production system, the Matrix 1.1, won’t ship till the second half of this year. That tool will have over 1,000 beams and run at 1 wafer per hour (as opposed to the 0.002 wph throughput of the current demonstration system). As with EUV, getting tools with sufficient throughput to enable development is a critical milestone.

I attended a few talks on metrology and resist materials related to line-edge roughness (LER). They reported small progress, but nothing even close to a breakthrough in either understanding or performance. LER remains a tough nut to crack.

With several sessions, about 70 papers, a panel, and a short course devoted to directed self assembly (DSA), this topic has definitely turned a corner at the conference. But with success comes an inevitable problem: commercial papers. I heard many complaints from people about papers describing the benefits of “polymer A” over “polymer B”, graphs with no axes numbers, and papers meant to impress rather than inform. It is certainly a high price of success to trade integrity for profit.

There were some great papers at AL on Tuesday. Here are some of my favorites. Peter Trefonas of Dow created a photosensitive block copolymer using a class of molecules called bottle brush polymers. This very early work nonetheless exhibited very good results – close to 20 nm resolution (e-beam litho) with nearly the first bottle of stuff they mixed up. The idea is simple: marry the high resolution and high sensitivity of chemically amplified photoresists with the low line-edge roughness and good CD uniformity of self-assembled block copolymers. Cool. And it looked like great fun for the chemists.

Julius Santillan of the EUVL Infrastructure Development Corp in Japan wowed the metrology conference with a high-speed atomic force microscope (AFM) that could measure 32-nm line/space features in situ during development using a carbon nanotube fiber cantilever in tapping mode. With a scan time of 2 seconds (faster is possible, he says) for a pixel size of 2.5 nm and an area of 1000nm X 750nm, the tool made absolutely remarkable movies showing resist development and roughness formation in several different kinds of resists. The difference between PHS-based EUV resists and methacryl-based EUV resists was startling. The impact of resist development on LER was clear for all to see. Now the challenge is how best to use this new view into the physics of LER formation.

The progress in directed self-assembly (DSA) since last year has been remarkable, as evidence by the number of papers on the topic this year if nothing else. The science is advancing, the technology is advancing, and the practice is advancing. We can make very tight pitch lines and spaces with DSA, but how can we cut them to make circuit patterns? Why, with DSA of course! Even better than small lines and spaces, DSA is good at making small contact holes (though not on a super-tight pitch). So the topic that most caught my attention today was the idea of using DSA-shrunk contact holes to the cut the DSA lines. The 14/10nm node(s) could be made with two 193i patterning steps (and thus only two masks), but with significant design/layout impact. This is a very, very interesting approach. I think we will hear much more about this in the next year.

As the afternoon turned to evening I went from a panel discussion on DSA to the poster session, with a “super panel” pulling in all the conferences still in store. But when the good beer ran out at the poster session, I took the opportunity to retire for the evening and let Aki Fujimura buy me an expensive dinner (thank you, Aki!). And there is still that pesky business of getting my talks ready for Wednesday. Yes, this is life at the Advanced Lithography Symposium.

Day 1 of the SPIE Advanced Lithography Symposium began, as always, with the plenary session. Bill Arnold, former lithography manager at AMD and now CTO at ASML, gave a “state of the union” address – he is this year’s SPIE president. (Congratulations, Bill – I voted for you!) The 10th Zernike Award for achievements in microlithography went to Dave Markle, a well-deserved honor (full disclosure: I nominated Dave, so my opinion may be biased). And SPIE inducted some of its newest members into the ranks of SPIE Fellow: Yan Borodovsky of Intel, Alain Diebold of the University of Albany, Kafai Lai of IBM, Bryan Rice of SEMATECH North (is there a SEMATECH south?), and Martin Richardson of the University of Central Florida. Congratulations to all.

The first plenary talk was by Bill Siegle on a topic very dear to me – the history of lithography. Bill spent many years at IBM and AMD, and keeps his hands in the industry as a member of the ASML board of advisors. (I was glad to see that he kept his ASML promotion to a bare minimum – only a couple of slides.) I especially liked his description of an internal step-and-repeat tool development project at IBM in the early 70s – the 5XLFS. It was a “dismal failure” and “generated a lot of scrap”. The industry was finally reaching the point where process equipment was best supplied externally rather than internally. The first commercial stepper, the GCA DSW 4800, could “predict the weather” due to its high sensitivity to barometric pressure. He provided many good lessons from this history, but I like #6 best: It’s impossible to predict 10 years ahead. I agree, but somehow it doesn’t stop me from trying.

Howard Ko of Synopsys gave a benign talk on the evolution of EDA (electronic design automation), and Chuck Szmanda gave an interesting talk on patent law (cheers to the selection committee for picking an unconventional plenary topic).

By 11am the technical sessions had begun. I went to see my good friend Mark Smith give a great talk (yes, I am biased) with an even better title: “Optimization of a Virtual EUV Photoresist”. There are so many ways to play on that title, but I’ll just say that I love virtual photoresists. They don’t smell.

The most important talk of the day (IMHO) was given by Sam Sivakumar of Intel. He presented results on working 22-nm SRAM devices (the first?) manufactured with EUV on the NXE:3100. EUV was used on two levels (a “line-like” layer and a “hole-like” layer, whatever that means) and the manufacturing performance of the 22-nm SRAM test vehicle was compared to standard 193-nm manufacturing. The devices worked well (though I didn’t understand the meaning of the device characteristics plots that he presented, since they had no axes labels), and this was an important milestone. Of course, the throughput was extremely low, but the point of the exercise was to test everything else about the manufacturing readiness of EUV. Wafer defect was only about 10 – 20X higher than the mature 193-nm process (not unexpected at this stage of development), and no killer mask defects were present. Sam showed a slide that said one undetected adder defect on the reticle could cost Intel $5M/day, so this is important. Overall, Intel seemed happy with the results.

But let’s keep things in perspective. This is a 22-nm SRAM test vehicle, which for Intel means the gate level is at a 90-nm pitch. Thus, the device is not sensitive to reticle defects that are beyond today’s inspection sensitivity but will be critical before EUV goes into production. Further, this test does not stress the EUV RLS triangle of death (the ugly trade-off between Resolution, Line-edge roughness, and Sensitivity that currently would kill any hope of economic manufacturing with EUV). This work had to happen, and I applaud Intel for publishing it (I hope Samsung and the other NXE:3100 owners will do the same). But it is not an existence proof for the manufacturability of EUV “if only we had a source”. It will take much more.

For the rest of the day I hopped from room to room trying to learn everything I could about line-edge roughness (LER)/linewidth roughness (LWR). I am happy to see that there are many more papers on that topic this year. On this first day the emphasis of most of them seemed to be on the importance of post-processing for LWR reduction. But here is my dilemma: 1) low-frequency LER causes an increase in CD non-uniformity, especially for contacts but for short-width gates as well; 2) this problem will be devastating to EUV lithography if low-frequency LER isn’t reduced significantly; and 3) LER post-processing won’t help with this problem since it does not (cannot) reduce low-frequency LER. Point #3 is where there may be some controversy (meaning that not everyone has come to see things my way). So here is my challenge to all those promoting the use of LER post-processing: prove to me that I am wrong by either convincing experimental evidence that low-frequency LER is reduced or a convincing proposed mechanism, and preferably both. Actually, I need both, and I haven’t seen it yet.

Finally, a soap-box moment (something that many of you know I am fond of). When is it OK to describe your idea as “new” when giving a paper? Here is a new theory, a new mechanism, a new approach, a new design. My advice: probably never. If your idea is truly new, then astute attendees of your talk will realize it. It’s OK to tell them why the problem you are working on is important, or why a solution to that problem is important. But don’t tell then that your work is important – that is a judgment they should make for themselves. I know that this advice is opposed to what every marketing professional will tell you, but we are not marketing people, we are scientists and engineers. And besides embracing the important ethic of humility, it is much safer not to claim that your idea is new for the simple reason that it probably isn’t. There is very little new under the sun, even though novelty is what advances science and why we are all at conferences like this one. None of us are familiar with everything in the literature, and an explicit claim of novelty can result in a swift rebuttal by someone pulling out an obscure (or not so obscure) reference to prove you wrong. Let the audience judge the novelty of your idea, and when you’re confronted with an old reference that did the same thing as you, you can be happy for the education and the knowledge that someone else has validated your idea.

Welcome to San Jose and the beginning of the Advanced Lithography Symposium. The last year seemed to zip by in hurry, and it was an interesting one. The lithography year 2012 was dominated by two big stories: progress in directed self assembly (DSA) and lack of progress in Extreme Ultraviolet (EUV) lithography. I’m anxious to hear the progress reports for each this week. For EUV, delays in the growth of source power are on everyone’s mind, but I’d like to point out that progress in the other essential areas of development are also under pressure. We are still mostly blind when trying to assess the defectivity of EUV reticles compared to spec, and resist line-edge roughness (and the CD Uniformity loss caused by it) is barely budging. Every year that EUV is delayed means that these specs must scale with the new resolution goal (will EUV be ready for the 8/7-nm node?), and we are still not sure if the 22-nm node specs can be met.

The conference this year is certainly on track to be a success. The attendance looks to be about the same as last year (1500 paid attendees, 2300 including exhibitors and exhibit-only attendees). The biggest conference this year is the Metrology conference (122 papers), and the smallest is the Design for Manufacturing (DFM) conference (25 papers). I’m giving the keynote for the DFM conference on Wednesday, so even though it is small, please don’t miss it!

On a personal note, this month marks my thirtieth anniversary as a lithographer. Am I really that old? When I glance in the mirror, or get up with a sore back after too many hours in a conference chair, the answer seems depressingly clear. But when I think about how much fun I am having in the world of lithography I somehow don’t feel that old. I guess that is what really counts. And this week will certainly be great fun. Let the conference begin!

“We have experienced some delay in EUV, basically caused by delays in developing the light source”, said Peter Wennink, ASML’s financial chief.

With that understatement, ASML succinctly explained its rationale for offering $2.6B in cash (25%) and stock (75%) to buy San Diego-based Cymer, the leading developer of EUV sources. Over the last year, ASML has sent about 500 of their engineers to work at Cymer’s EUV source development labs. But as EUV source development falls further behind schedule, it has become obvious that this infusion of manpower was not enough.

There is a nice symmetry at work here. Earlier this year ASML got Intel, TSMC and Samsung to buy 23% of ASML and invest in ASML R&D to boot. Just as the chip makers invested in their key supplier ASML to provide maximum financial stability during a turbulent time, ASML is investing in one of its most critical suppliers to make sure they keep the faith during a very difficult time. Will this help speed up EUV source development? I doubt it. But it will probably help prevent a worsening of the schedule and keep Cymer’s focus where it needs to be.

While everyone concentrates on Cymer’s EUV source development, it is important to remember that ASML’s and Cymer’s cash cow is 193-nm immersion lithography. As ASML dumps cash into EUV development, it has remained profitable due to its growing market share of 193-nm tools (now about 80%). But Cymer only supplies about half of the 193-nm lasers that ASML needs. The other half comes from Gigaphoton (formed in 2000 as a joint venture of Komatsu and Ushio). What will happen to Gigaphoton in the long term? You can bet they are trying to figure that out themselves about now. And what does this deal say about ASML’s faith in Gigaphoton’s EUV source development efforts? It seems ASML is willing to put all of its source eggs in one basket.

Alas, I was not able to attend the Bacus maskmaking conference last week in Monterey, California. Although smaller now than in its heyday, it is still a fun conference to go to. But thanks to some talented and enterprising Baccanalians, a little of the flavor of the conference is available on YouTube:

http://www.youtube.com/watch?v=2HgJc9UMvd0&feature=share

I don’t know who all the folks are who made this, though I do recognize Mark Mason (the Aggie) and it must certainly be Tony Vacca on the drums.

For a little history on Bacus entertainment, look here.

After posting on Why 450-mm Wafers and Why the Big Players Like 450-mm Wafers, I received a few comments from friends in the equipment supplier community talking about the effect of wafer-size transitions on the suppliers of process and metrology tools for semiconductor manufacturing. So, based on their inputs and further reflection, here are a few more thoughts on 450-mm wafers.

It is expensive to develop equipment to process larger wafers. If an equipment supplier spends a boatload of money developing new equipment, they want to sell that new equipment for a lot of money in order to recoup their investment. But their customers, the chip makers, don’t want the equipment prices to rise too much, or else the cost advantage of the larger wafer size will disappear. The goal should be a win-win sharing of the benefits of a lager wafer: the chip makers get a lower manufacturing cost per chip and the equipment makers get a higher margin on their equipment, thus paying off their R&D and making more money after that.

There is a general feeling in the industry that the transition to 300-mm wafers didn’t work out equitably: the equipment suppliers made all the investments, and the chip makers got all the benefits. And while I’m sure this version of the story is somewhat slanted, still we have seen most equipment suppliers dragging their feet on 450-mm tool development. They want the chip companies to pay up-front for development. Chip companies in turn want to get governments to foot the bill (why should a highly profitable company like Intel pay the costs needed to ensure future profits if they can get the state of New York to pay instead?). And so it has begun: the Global 450 Consortium funding tool R&D, and Intel, TSMC, and Samsung paying litho supplier ASML billions of dollars directly for 450-mm tool development.

How will a transition to 450-mm wafers affect the equipment suppliers? One effect is similar to that experienced by the chip makers: the small guys won’t survive. Only the bigger players can afford the development costs for 450-mm wafer size tools. But there has traditionally been a second effect: even the big players can’t afford the development costs of new process equipment on multiple wafer sizes.

When the industry moved to 300-mm wafers, new process tools were developed for 300-mm wafers only. Chip companies that stuck to 200-mm wafers couldn’t get the latest and greatest tools for the smaller wafer size. They were stuck in the past. Not only did they have a cost disadvantage compared to 300-mm fabs, they had a technology disadvantage as well. Staying up to speed on Moore’s Law required moving to 300-mm wafers.

Will the same thing happen at 450 mm? Maybe, but I’m not convinced that it is inevitable. As I said before, the move to 450-mm wafers will not likely be the slam-dunk cost savings that many people hope. If the cost advantage is only 10%, I suspect many companies will choose to stick with 300-mm wafers. But will the next generation of process tools be available at the smaller wafer size? If new 300-mm wafer fabs are being built, you can bet that equipment suppliers will scramble to provide them with tools.

All in all, I think the move to 450-mm wafers will be a mess. The timing is problematic, the economics are problematic, and the resemblance of the future to the past is not likely to be strong. Somehow, though, we’ll figure something out. We always do.

The reason semiconductor manufacturers like the idea of 450-mm wafers is easy to understand: bigger wafers should lower the per-chip cost of manufacturing. But as I mentioned in my last post, this per-chip cost advantage doesn’t apply to lithography. Each time a wafer size is increased, only the non-litho (per-chip) costs go down, and so lithography costs take up a bigger portion of the overall costs. A corollary to this economic reality is that as lithography costs go up as a fraction of the total costs, the benefits of a larger wafer size go down. Past wafer size transitions have netted a 30% manufacturing cost reduction. The transition to 450-mm wafers will give at best a 20% cost reduction, and possibly only a 10% reduction.

Of course, these numbers are projections, and all projections are based on assumptions. It is possible to make more optimistic assumptions than I have, and that is probably what Intel, TSMC and the other big players are doing when they heavily promote 450-mm wafers. But why are the big guys so optimistic about 450-mm wafers? And why now?

As I briefly mentioned in my last post, for the switch to larger wafer sizes to be economically feasible two things must happen. First, the switch must enable a lower manufacturing cost per chip. The big players are hoping for a 30% cost reduction, but I am predicting a 10 – 20% benefit. Second, there must be sufficient demand for the chips being produced to justify a higher volume factory. A 450-mm fab will have at least double the output (in terms of chips) as a 300-mm fab. Thus, the demand for those chips must at least double to justify the building of a 450-mm fab. That’s a huge volume of chips, since 300-mm fabs are already exceedingly high-volume.

So an important effect of each wafer transition is that low-volume manufacturers can no longer compete. A 30% cost disadvantage is hard to overcome, and without the volume demand a new fab at the larger wafer size isn’t justified. The result? A successful wafer size transition is accompanied by a host of consolidations and chip companies going fabless (or fab-lite). This has happened again and again over the years. Only the biggest players survive, and the survivors get bigger.

Today, we have Intel, Samsung, Toshiba and TSMC at the top of the chip-making pyramid. But UMC, GlobalFoundries, Hynix, and Micron remain competitive irritants. What to do? A successful transition to 450-mm wafers will likely solve the problem for the big players. If 450-mm wafers result in a 20 – 30% cost advantage over 300-mm wafers, then any standard-process chip in a cost competitive space will have to be made in a 450-mm fab. But only a few of these $10B fabs will have to be built to supply that demand. And those fabs will be built by the biggest players, leaving the second tier manufacturers out of luck, and possibly out of business.

So why shouldn’t Intel, Samsung, and TSMC be bullish on 450-mm? If it works, it will mean that their dominance in the semiconductor world will be complete (maybe even pushing Toshiba out of the picture). And if EUV succeeds in keeping litho costs down, this scenario is all the more likely.

But personally I don’t think EUV will be successful at putting a lid on litho cost. As a result, I think the cost advantage of 450-mm will be closer to 10% than the 20 – 30% hoped for by the big guys. And while 10% may still be worth it for the highest-volume players, it won’t be enough to put the 300-mm fab world out of business.

That leaves one more ugly point to consider. If a transition to 450-mm wafers gives a per-chip cost reduction that is not sufficiently large to counter the rising costs of litho, then the per-chip costs overall might be higher (and maybe a lot higher) for new technology nodes. What will happen to Moore’s Law if moving to the next node no longer decreases the cost of a transistor?

We live in interesting times, and getting more interesting each day.

Why is 450-mm development so important to Intel (and Samsung and TSMC)?

A few years ago, Intel and TSMC began heavily promoting the need for a transition from the current standard silicon wafer size, 300 mm, to the new 450-mm wafers. While many have worked on 450-mm standards and technology for years, it is only recently that the larger wafer has received enough attention and support (not to mention government funding) to believe that it may actually become real. While there has been much talk about the need for a larger wafer, I’d like to put my spin on the whole debate.

First, a bit of history. Silicon wafer sizes have been growing gradually and steadily for the last 50 years, from half-inch and one-inch silicon to today’s 300-mm diameter wafers. The historical reasons for this wafer size growth were based on three related trends: growing chip size, growing demand for chips, and the greater chip throughput (and thus lower chip cost) that the larger wafer sizes enabled. And while chip sizes stopped increasing about 15 years ago, the other two factors have remained compelling. The last two wafer size transitions (6 inch to 8 inch/200 mm, and 200 mm to 300 mm) each resulted in about a 30% reduction in the cost per area of silicon (and thus cost per chip). And since our industry is enamored with the thought that the future will look like the past, we are hoping for a repeat performance with the transition to 450-mm wafers.

But a closer look at this history, and what we can expect from the future, reveals a more complicated picture.

First, how does increasing wafer size lower the cost per unit area of silicon? Consider one process step as an example – etch. Maximum throughput of an etch tool is governed by two basic factors: wafer load/unload time and etch time. With good engineering there is little reason why these two times won’t remain the same as the wafer size increases. Thus, wafer throughput remains constant as a function of wafer size, so that chip throughput improves as the wafer size increases. But “good engineering” is not free, and it takes work to keep the etch uniformity the same for a larger wafer. The larger etch tools also cost more money to make. But if the tool cost does not increase as fast as the wafer area, the result is a lower cost per chip. This is the goal, and the reason why we pursue larger wafer sizes.

As a simplified example, consider a wafer diameter increase of 1.5X (say, from 200 mm to 300 mm). The wafer area (and thus the approximate number of chips) increases by 2.25. If the cost of the etcher, the amount of fab floor space, and the per-wafer cost of process chemicals all increase by 30% at 300 mm, the cost per chip will change by 1.3/2.25 = 0.58. Thus, the etch cost per chip will be 42% lower for 300-mm wafers compared to 200-mm wafers.

While many process steps have the same fundamental scaling as etch – wafer throughput is almost independent of wafer size – some process steps do not. In particular, lithography does not scale this way. Lithography field size (the area of the wafer exposed at one time) has been the same for nearly 20 years (since the era of step-and-scan), and there is almost zero likelihood that it will increase in the near future. Further, the exposure time for a point on the wafer for most litho processes is limited by the speed with which the tool can step and scan the wafer (since the light source provides more than enough power).

Like etch, the total litho process time is the wafer load/unload time plus the exposure time. The load time can be kept constant as a function of wafer size, but the exposure time increases as the wafer size increases. In fact, it takes great effort to keep the scanning and stepping speed from slowing down for a larger wafer due to the greater wafer and wafer stage mass that must be moved. And since wafer load/unload time is a very small fraction of the total process time, the result for lithography is a near-constant wafer-area throughput (rather than the constant wafer throughput for etch) as wafer size is changed.

One important but frequently overlooked consequence of litho throughput scaling is that each change in wafer size results in an increase in the fraction of the wafer costs caused by lithography. In the days of 6-inch wafers, lithography represented roughly 20 – 25% of the cost of making a chip. The transition to 200-mm (8-inch) wafers lowered the (per-chip) cost of all process steps except lithography. As a result, the overall per-chip processing costs went down by about 25 – 30%, but the per-chip lithography costs remained constant and thus become 30 – 35% of the cost of making a chip.

The transition to 200-mm wafers increased the wafer area by 1.78. But since lithography accounted for only 25% of the chip cost at the smaller 6-inch wafer size, that area improvement affected 75% of the chip cost and gave a nice 25 – 30% drop in overall cost. The transition to 300-mm wafers gave a bigger 2.25X area advantage. However, that advantage could only be applied to the 65% of the costs that were non-litho. The result was again a 30% reduction in overall per-chip processing costs. But after the transition, with 300-mm wafers, lithography accounted for about 50% of the chip-making cost.

Every time wafer size increases, the importance of lithography to the overall cost of making a chip grows.

And there lies the big problem with the next wafer size transition. Each wafer size increase affects only the non-litho costs, but those non-litho costs are becoming a smaller fraction of the total because of wafer size increases. Even if we can achieve the same cost savings for the non-litho steps in the 300/450 transition as we did for the 200/300 transition, its overall impact will be less. Instead of the hoped-for 30% reduction in per-chip costs, we are likely to see only a 20% drop in costs, at best.

So we must set our sights lower: past wafer size transitions gave us a 30% cost advantage, but 450-mm wafers will only give us a 20% cost benefit over 300-mm wafers. Is that good enough? It might be, if all goes well. But the analysis above applies to a world that is quickly slipping away – the world of single-patterning lithography. If 450-mm wafer tools were here today, maybe this 20% cost savings could be had. But shrinking feature sizes are requiring the use of expensive double-patterning techniques, and as a result lithography costs are growing. They are growing on a per-chip basis, and as a fraction of the total costs. And as lithography costs go up, the benefits of a larger wafer size go down.

Consider a potential “worst-case” scenario: at the time of a transition to 450-mm wafers, lithography accounts for 75% of the cost of making a chip. Let’s also assume that switching to 450-mm wafers does not change the per-chip litho costs, but lowers the rest of the costs by 40%. The result? An overall 10% drop in the per-chip cost. Is the investment and effort involved in 450-mm development worth it for a 10% drop in manufacturing costs? And is that cost decrease enough to counter rising litho costs and keep Moore’s Law alive?

Maybe my worst-case scenario is too pessimistic. In five or six years, when a complete 450-mm tool set might be ready, what will lithography be like? In one scenario, we’ll be doing double patterning with EUV lithography. Does anyone really believe that this will cost the same as single-patterning 193-immersion? I don’t. And what if 193-immersion quadruple patterning is being used instead? Again, the only reasonable assumption will be that lithography accounts for much more than 50% of the cost of chip production.

So what can we conclude? A transition to 450-mm wafers, if all goes perfectly (and that’s a big if), will give us less than 20% cost improvement, and possibly as low as 10%. Still, the big guys (Intel, TSMC, IBM, etc.) keep saying that 450-mm wafers will deliver 30% cost improvements. Why? Next time, I’ll give my armchair-quarterback analysis as to what the big guys are up to.

OK, I have to admit this right off: I didn’t go to Semicon West (held two weeks ago in San Francisco). I try never to go to Semicon West (I’ve been twice in the last 30 years, both times against my will). Why should I go? To listen to the latest marketing messages and company spin? To see a few technical talks that are way too light on the technical, but still full of talk? I don’t need to walk the cavernous Moscone Center to get that – everybody plasters the Web with this stuff on a regular basis. Thanks, but I think I’ll stay home.

This year was a perfect case in point. The only real news from Semicon was in the news – Intel’s announced investment in ASML. Yes, it would have been fun to sit in a San Francisco bar each evening and dissect the press releases and develop conspiracy theories. But even that is not really necessary. I’m here to give my you take on what the Intel investment means – and you don’t even have to buy me a beer to get it. (Though if you like this post, please feel free to buy me one the next time you see me.)

Intel’s investment in ASML has two parts – related, but separate. First, Intel is spending $2.1B to buy 10% of ASML, with an option to buy another 5%. ASML will use the money to buy back the same number of its shares, so there will be no stock dilution (a so-called synthetic buyback). That also means ASML will be getting nothing (no money, I mean) from this part of the deal. ASML is also offering similar deals to Samsung and TSMC, up to 25% ownership in the company. So what does this part of the deal mean? Intel and ASML made it clear that Intel gets no voting rights and won’t get early access to ASML technology or tools. Of course, they had to say that to avoid anti-trust litigation. So does the Intel investment help anyone?

There are three reasons why the Intel investment in ASML makes sense. First, it confirms the obvious: the success or failure of ASML will be mirrored as success or failure at Intel. Lest anyone doubt it, Intel needs Moore’s Law scaling to continue its growth and profitability. Lithography is the critical technology to make that happen, and ASML is the critical company to make lithography happen. Second, even without a place on the board, Intel’s ownership stake will add financial stability to ASML, whose stock price could easily drop dramatically if its EUV program were to flirt with failure. Since ASML’s importance to the industry goes far beyond its EUV program, keeping ASML developing and manufacturing lithography tools is critical.

But the third reason the investment makes sense is that the stock purchase is coupled with a $1B Intel investment in ASML R&D. This $1B infusion is what the whole deal is about, and the investment has one purpose: to speed 450-mm tool development at ASML. For several years now, as talk of 450-mm wafer sizes has heated up to what appears to be a critical mass, ASML has repeatedly said that it can’t do EUV and 450-mm development at the same time. After EUV has succeeded, then ASML will commit to 450-mm tool development. But since the day of reckoning for EUV continues to push out (possibly to 2016 or later), that means lithography, representing 50% of the cost of making a chip, won’t be 450-mm ready nearly in time to meet the (overly optimistic) timetables of the big 450-mm proponents (Intel, Samsung, and TSMC).

So here comes the investment from Intel. While the press release mentioned the importance of both EUV and 450-mm R&D, the only project mentioned for funding was 450-mm tool development. And to be clear, this is not only, or even mostly, EUV 450-mm development. A working 450-mm fab will need 193-immersion tools, 193 dry tools, and maybe 248-nm tools as well, all running at the 450-mm wafer size. If EUV works, a fab will need 450-mm EUV tools as well, but this is the only part of the lithography tool set that is optional for a 450-mm fab. So, in my opinion, the Intel investment is all about the 450-mm wafer size, and has essential nothing to do with EUV lithography.

Why is 450-mm development so important to Intel (and Samsung and TSMC)? My answer to that question next time.