The first day of the symposium begins with the plenary session. I was excited to see Marc Levenson pick up the 7th Frits Zernike Award for Microlithography. Very well deserved recognition for his work in phase-shifting masks and wavefront engineering. [A quick medal count – IBM and IBM alum have 4, the rest of the world 3.] Five new SPIE fellows were inducted as well: Bob Allen, Jos Benschop, Cliff Henderson, Soichi Owa, and Jim Potzick. Congratulations!
The three plenary talks were all solid, but none were stand-out. Ushida-san of Nikon gave the best talk, though it had the predictable sales pitch for Nikon’s newest immersion scanner. I liked the way his talk was peppered with Japanese sayings (“The priest who preaches foul doctrine shall be reborn as a fungus.”). Nikon is finally correcting the NA gap in 193 scanners, bringing their highest NA up to 1.35 to match ASML. And since Nikon has been understandably unwilling to bet their company on EUV, they outlined a strategy for pushing 193 with double patterning to 22-nm half-pitch and a little below, making the 16-nm half-pitch node (which is NOT the 16-nm node) a contest between EUV and quadruple patterning. Quadruple patterning? Really?
I find it very interesting to see various players in the industry slowly getting behind this basic double-patterning strategy: Designs are restricted to essentially one-dimensional features of a single pitch on a grid. The first patterning step uses 193i with sidewall-spacer pitch doubling that can get the final pitch down to around 38 – 40 nm. A second patterning step then cuts the lines to make the final pattern. The resolution of the second patterning step determines the tip-to-tip spacing of the line patterns, but is a secondary (though important) influencer of packing density. What tool will do the cutting? Immersion with all the optical tricks? Multiple e-beams? EUV? Yes, Intel has proposed that the proper role of EUV may be to do the cutting of fine patterns made by 193 immersion. We live in a funny world.
With the start of the conference sessions I went to the resist conference and saw the invited talks. I was surprised to see in the talks one picture of me and one picture of my Lotus (actually a stand-in picture – my Lotus is red). It’s important to have good jokes in an invited talk, I suppose. John Sturtevant of Mentor talked about the compute load for model-based OPC. At the 130-nm node one layer required model-based OPC, and that took about 200 CPU hours. At the 16-nm node, we expect 50 layers to need MBOPC and each of those require 200,000 CPU hours. That’s a hefty compute load. In the afternoon I saw a couple of resist papers on LER, but not much that made me sit up and take note.
All-in-all, the conference is off to a good start.
The Texas Two-Tone resist was termed the most important development in the last 10 years in a comment by Will Conley of Freescale Semiconductor, a recognized industry expert. It does seem more likely to be used in production than resists that require two developers to print both tones: one aqueous and one an organic solvent.
The key idea of Holistic Lithography, according to Bert Koek, senior vice president of the applications products group at ASML, is integrating computational lithography, wafer printing, and process control to enable shrink towards 32nm using 193nm water immersion exposure tools.
I find it very interesting to see various players in the industry slowly getting behind this basic double-patterning strategy: Designs are restricted to essentially one-dimensional features of a single pitch on a grid. The first patterning step uses 193i with sidewall-spacer pitch doubling that can get the final pitch down to around 38 – 40 nm.