SPIE Advanced Lithography Symposium 2010 – day 4

The “hottest ticket” of the week were the ASML and Cymer updates on EUV lithography progress. It was beyond standing room only for the ASML talk, with a line out the door of the conference room. I decided not to brave the crowds, since I knew what was going to be said: everything is going even better than expected; the project is on-time and according to plan; EUV is inevitable. I poked my head in for the Cymer update on building sources for the ASML preproduction tool (PPT). They have six sources under construction, but unfortunately they will ship with an expected output of 40W, 20% of the 200W required for the PPT to have a chance of meeting its 60 wafer per hour throughput goal. They plan to upgrade the source in the field in two steps, first to 90W and then to the final 200W. Challenging, to say the least. Of the three technologies that could easily kill EUV lithography, source power is the most obvious and thus will probably get blamed when EUV dies (the other two problems are resist performance and mask defectivity, both of which will also take much longer to solve than the industry’s timetable demands).

As I come to the end of the week, I start thinking of summing up my impressions of another Advanced Lithography Symposium. I attended only about 20% of the 340 oral papers presented this year, so my sampling is certainly far from comprehensive. Hopefully, though, my posts this week have given an accurate impression of the conference nonetheless. Several people mentioned to me that they were impressed with the progress being made on directed self-assembly polymers – it’s moving beyond a science project to become an engineering project, and the results are looking good.

Since I have complained repeatedly in past years about lying with graphs (no numerical labels, misleading axes ranges that hide variations, etc.), I seem to have created an informal graph-police among my fellow lithographers who alert me to what they consider to be the most egregious abuses. One new complaint: displaying two wafer maps and then claiming that the spatial signatures are correlated because they look similar. But why do ‘chi-by-eye’ when performing a real correlation, with a scatterplot and a correlation coefficient, is trivial to do? Is there something to hide, or is the author just being lazy?

Finally, here are some of my favorite quotes from the conference. First, the bar quotes – gems from lithographers with a beer in their hand:

“You spend $120M on an EUV scanner. The result? You get a space with three more photons than a line.” (From an engineer worried about line-edge roughness.)

“I just spent 18 hours exposing one sh!$ty wafer with EUV.” (A student talking about collecting experimental data on the ASML ADT.)

And finally, quoting myself speaking directly to the audience during my line-edge roughness talk” “Your LER metrology sucks.”

And so ends another intensive week of talking, thinking and drinking about lithography. I love this conference!

One thought on “SPIE Advanced Lithography Symposium 2010 – day 4”

  1. The chip industry continues to name lithography as a critical challenge in fabricating next generation integrated circuits, and never before has this been so true.

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