The first day of the symposium began with the awards. I was very happy to see a great group of new SPIE fellows from our community: Emily Gallagher of Imec, Yuri Granik of Mentor Graphics, Qinghuang Lin of IMB, David Pan of the University of Texas at Austin, Mark Phillips of Intel, and James Thackeray of Dow. Congratulations to each of you for this well-deserved recognition. Donis Flagello, CEO of Nikon Research Corporation of America, won this year’s Frits Zernike award (full disclosure, I nominated him). For a history of the Zernike award, see this brief article.
For a change, I enjoyed all three plenary speakers. Usually, at least one is a dud, but not this year. I have to admit that I didn’t care for JSR CEO Nobu Koshiba’s disciple-like references to Ray Kurzweil and his singularity predictions (I’m not a Kurzweil fan), but it was just one part of his overall optimism for Moore’s Law. I don’t agree that Moore’s Law will continue to the 2-nm node, but I guess it’s important that sufficient optimism exists, otherwise we’ll never try. And we should try.
The first two talks of the EUV session were keynote addresses. Britt Turkot of Intel painted a fairly rosy picture of the progress of EUVL towards manufacturing readiness. “It’s been a long and winding road,” and we still have a ways to go, but the eight NXE:3300s and six NXE:3350s in the field are giving semiconductor manufacturers opportunities to shake out enough of the reliability problems to enable process learning. Tool availability continues to creep up (past the 70% mark), and mask making has progressed to the point where Intel has made “multiple” defect-free EUV masks. Intel showed data on “adders” (defects that get added to the mask during use) and reiterated their message from last year that that production without a pellicle is not an option. Thus, it makes sense that she listed the availability of a manufacturing-capable pellicle as the biggest risk.
She also mentioned stochastics, saying that “CD and edge placement variability is a deal breaker.” But then her conclusion slide said that resist performance won’t gate the introduction of EUV. I didn’t know what to make of these mixed messages, especially when she explained that the target dose for EUV manufacturing was 20 mJ/cm2. At that dose, there will be plenty of CD and edge placement variability.
Seong-Sue Kim of Samsung was similarly encouraged by EUVL improvement. He expressed amazement at the progress in mask blank defectivity saying it had reached the benchmark of 5 defects per blank that he thinks can enable manufacturing. He also said that the mask blistering problems he mentioned last year have largely been solved. For resists, he thinks that current performance is good enough for 7nm development, but sensitivity (at low roughness) needs to be improved for production. Of course, everyone agrees with that statement. The question is how to do it.
My favorite technical talk was Bill Hinsberg’s modeling of metal-oxide resists – a much needed start. John Biafore gave a great paper modeling millions of contact holes at various EUV conditions and looking for stochastic-related failures. He expressed skepticism at any possible breaking of the RLS trade-off (“resolution, LER, sensitivity – pick two”).
Finally, I was extremely gratified by the reception I received to my tutorial talk and was grateful for the many people willing to stay till 6:30pm to hear me speak. Thanks to Eric Panning and Ken Goldberg and the EUV Lithography conference for giving me such a great opportunity to talk about stochastic-induced roughness.
2 thoughts on “SPIE Advanced Lithography Symposium 2017 – day 1”
Great post Chris, keep us updated!
Thank you Chris. This is always the best gift for us lithgraphyers every year.