Tag Archives: SPIE

SPIE Advanced Lithography and Patterning Symposium 2022 – day 4

The mood at the conference this week can be summed up in one word:  happy.  We were all just happy to be here, with smiles visible everywhere, even under masks.

Thursday morning began with a quite philosophical keynote talk in the metrology session on the role of MI (metrology and inspection) in semiconductor manufacturing by Younghoon Sohn of Samsung.  He touched on broad subjects like the role of sampling (depends on the failure rate), the dilemma between resolution and speed in inspection (and the wide gulf in both between optical and e-beam inspection), and the basic roles of MI (define a process window, identify cause and effect, and process monitoring and control).

A joint session between Optical/EUV and Etch provided several nice papers.  Angelique Raley gave an overview of three techniques being promoted by TEL:  a spin-on SiC underlayer for EUV to prevent pattern collapse, a development process (not really explained) called ESPERT for Inpria resists that also prevents pattern collapse by improving the sidewall profile, and a cryogenic etch for lower LCDU (local critical dimension uniformity) and defectivity.  Roberto Fallica of imec gave a quote that I like (and often say myself), “Stochastics is the major roadblock for EUV Lithography”.  He then talked about a “healing” etch process that reduces contact hole LCDU through an aspect ratio dependent etch rate (high aspect ratio resist patterns etch faster, causing narrow holes to widen, while low aspect ratio resist patterns etch mode slowly, causing wide holes to narrow).  One interesting (and confusing) result was that the dose that provided smallest LCDU was not the dose that gave the lowest defectivity.  Finally, Qinghuang Lin of Lam talked about the application of Lam’s new dry-deposited and dry-developed resist to contact holes (I was not able to catch Rich Wise’s earlier paper on its application to lines and spaces).

Since I left after lunch to catch a plane home, I was not able to see what I’m sure were some good papers on the last afternoon of the symposium.  After a valuable and rewarding week here in San Jose, I was still anxious to get home.  Looking back two years, here is how I ended my Advanced Lithography Diary in February of 2020:

“The week has also seen an escalating concern over the new coronavirus, COVID-19.  Like everyone else I am monitoring developments with morbid fascination, but also to see how it will impact my immediate future.  And it has.  If there is any positive to the spreading fear over the spreading virus, it is that I will soon be traveling far less.  I have started asking customers if we could schedule our meetings, demos, and courses using video conferencing rather than in-person, and they are readily agreeing.  Maybe such accommodations will be a permanent trend, with the significant savings in time and resources that come with less travel (not to mention a better quality of life when I spend more time with my family).  I will look to this thought as a small consolation.”

That prediction proved true.  Like everyone, I have spent much of the last two years living my life on Zoom.  But since my life before the pandemic involved far too much travel, I am grateful for the respite that the pandemic forced upon me.  I am very glad to be back at ALP live and in person, and am glad that I can start visiting customers again (most of them, anyway).  But the much-accelerated use of video meeting technology has permanently changed the way I do business, and I am happy for the family time it will enable.  Like most of us, this pandemic has triggered a reckoning in my life/work balance, and I am happy for the result.

So, for those of you who wanted to but could not come to San Jose this week, I hope to see you next year.  But if not, maybe I’ll see you on Zoom.

SPIE Advanced Lithography and Patterning Symposium 2022 – day 3

In the morning, the optical and EUV session included two very good talks on EUV pellicles.  Mark van de Kerkhof described ASML’s latest material, a composite made of metal silicide crystals (if I got that right) that performs just a little bit better than the prior polysilicon-based stack.  At almost 92% transmission (one pass), it is a few percent better than the previous best and survives up to 400W source power.  Is it good enough to be adopted in manufacturing?  I’m not sure.  The next talk by Lintec described a 95% transmitting carbon nanotube pellicle, quite a promising result.  Their pellicle is making progress but did not seem manufacturing ready, requiring a bit more time to mature.

In the metrology session, my colleagues Gian Lorusso and Mohamed Zidan from imec gave a pair of good talks on the metrology challenges for measuring very thin resists.  (Full disclosure – I was a coauthor on both papers.)  When the as-coated resist thickness reaches 10 nm, line/space patterns have almost no contrast in a SEM, making measurement of CD and LWR extremely difficult.  Lowering the SEM voltage to 300V, and even lower for some materials, improved things.  It looks like 15 or 20 nm thickness and above is manageable with the right SEM measurement conditions.

I was also very impressed by Nearfield Instruments and their high throughput AFM, described by Cornel Bozdog.  Using four AFM heads running in parallel they could measure 64 0.5micronX0.5micron regions per wafer and get a throughput of 12 wafers per hour.  While I’m sure the typical “your results may vary” caveat applies, it is still an order of magnitude faster than I would have expected.

Quite a few students are attending the conferences this year, and I’ve been able to meet some of them.  Seeing the look of these eager young people, drinking from the firehose of information pouring out in each of the sessions, makes me hopeful for the future of our industry.

SPIE Advanced Lithography and Patterning Symposium 2022 – day 2

The first talk of the metrology conference on Tuesday was by Andras Vladac of NIST on a topic I am very interested in – characterizing the non-ideal behavior of scanning electron microscopes.  His presentation style was somewhat unique:  taking the material from what appeared to be a half-day short course and presenting it in 20 minutes.  This is a definitely a talk where viewing and studying it later (thanks to SPIE’s recording) is a must.  The other talks in the SEM session were good as well, but more digestible.

Tuesday was packed with customer meetings for me – a mixed blessing.  I missed many good talks, but got to have facetime with people I had not been able to visit for at least two years.  I managed to catch the end of Erik Hosler’s plenary talk in the afternoon on “The path to a useful quantum computer”.  One of the more interesting insights was his need to use state-of-the-art immersion lithography for the fabrication of his devices, not for the resolution but for the precision of the manufacturing.  For an optical device, feature sizes are in the hundreds of nanometers or microns.  But quantum optical devices require on the order of 1 nm line-edge roughness from those features, which definitely pushes state-of-the-art capabilities and makes fabrication quite challenging.

SPIE Advanced Lithography and Patterning Symposium 2022 – day 1

As always, the opening of the symposium began with some awards.  Our community’s biggest and most prestigious is the Frits Zernike Award for Microlithography, and it was wonderful to see Harry Levinson receive this year’s honor.  (Full disclosure – I’m on the award selection committee.)  Additionally, since last year’s award ceremony was virtual, Bruce Smith was giving his 2021 Frits Zernike Award for Microlithography as well.  Congratulations to them both!

Four presentations of SPIE fellow were made next:  Nelson Felix of IBM, Kevin Lucas of Synopsys, Uzodinma Okoroanyanwu of the University of Massachusetts, and Tatyana Sizyuk of Argonne National Laboratory.  It’s a shame that Kevin and Uzo could not be here this week.

We next heard two of the three plenary talks (Eric Hosler’s talk on quantum computers will be given on Tuesday.)  The first talk was by Luc Van den hove, President and CEO of imec.

A quick digression.  We have had over the years a number of plenary talks given by various industry executives covering topics of interest to our community such as compute scaling, artificial intelligence, the automotive industry, progress in GPUs, etc.  My biggest fear for these kinds of speakers is getting what I call the “kid on a skateboard” talk.  The executive, giving the same talk they might give at an investor conference, says things like “Technology A is very important” while showing a kid on a skateboard, “Our company is ahead on technology B” then shows a family playing with a dog, etc.  Very slick, and devoid of useful content.  So when a CEO is asked to give a talk on a Wall Street-friendly topic such as “The endless progress of Moore’s Law”, I usually get worried.

But Luc Van den hove is not your typical CEO.  He is a lithographer deep in his bones.  He published his first SPIE paper in 1990, and was chairman of the Optical Microlithography conference in 1998 and 1999.  He knows what he is talking about, and cares deeply about this community.  So when the first few slides in his talk were of the “kid on a skateboard” variety, I was not worried.  He soon got into the technical meat of the topic, and we were all rewarded for our patience.  Taking the broad view of what Moore’s Law means that is typical of today, he described four general areas that will keep progress in semiconductors moving for quite some time (though not the hyperbolic “endless”):  Shrinking the transistor, improving the transistor, moving into the third dimension, and shifting compute paradigms.  I suspect that he is correct on all counts.

The second plenary by H.S. Philip Wong of Stanford went into considerably more detail on two of Luc’s topics, system-level optimization and 3D integration.  Dr. Wong is an expert on these topics and I learned quite a bit.  He would have been better off, however, if he had not tried to force lithography relevance into his talk through his provocative title and subsequent discussion of EUV lithography throughput (Tony Yen – you were a bad influence!).

For the rest of the day I alternated between the metrology conference and the two keynote talks at the Optical and EUV Nanolithography conference.  Nelson Felix gave a nice review of metrology needs for nanosheet transistors, though I was very surprised when he showed that 1/3 of all the process steps in IBM’s latest generation process were metrology steps, and that this hasn’t changed since the 45 nm node.  There is no doubt that IBM does more metrology than your typical fab.  Mark Phillips of Intel gave a very optimistic view of when high-NA EUV lithography could be inserted into manufacturing, beating by a year the roadmap shown by Luc Van den hove (which, coming from imec, could also be assumed to be optimistic).  It sounds to me that Intel is tired of being behind in EUV and is hoping that high-NA EUV will give them a chance to leapfrog ahead.

I ended the day with a Fractilia hospitality event at a favorite San Jose brew pub.  Thanks to all who joined us!

SPIE Advanced Lithography and Patterning Symposium 2022 – day 0

“The SPIE Advanced Lithography conference begins with one word on everyone’s mind:  coronavirus.”  These are the first words I used in my blog post two years ago, just as the SPIE Advanced Lithography Symposium of 2020 was about to begin on February 23.  I had no way of knowing that within three weeks pretty much the whole country would start locking down.  That 2020 conference went off without any known coronavirus transmissions, thank goodness, and two+ years later I think that first sentence applies equally well today.  Last year’s symposium was virtual, and this year’s has been postponed two months, just long enough to allow the Omicron variant to fad and for most of us to gather with more confidence.

It’s good to be live and in-person!  I’ve already seen on Sunday several folks that I have only seen on Zoom for the last two years, and it is a great pleasure!  The conference is promising to be a good one, effected though it is by the lingering impact of the pandemic.  Virtually no one from Taiwan, Korea, or Japan has been able to attend, and participation from Europe is down significantly.  Still, registration currently sits at 1,300 (as opposed to the pre-pandemic average of about 2,000), which is better than I was expecting.  There were 390 paper submissions this year (in 2020, the number was about 500) and I’m hoping for a very good program.

There have been a couple of major changes in the symposium this year.  The EUV and Optical Lithography conferences have merged (now called Optical and EUV Nanolithography), reflecting the continued mainstreaming of EUV lithography out of development and into semiconductor manufacturing.  The topic of computational lithography, formerly homed in the Optical Lithography conference, now resides in the refocused DTCO and Computational Patterning conference.  These are both good changes, and I look forward to seeing how they play out this week.

SPIE Advanced Lithography Symposium 2016 – a prologue

2016 will prove to be a pivotal year in the history of semiconductor lithography.  How do I know this?  Because every year proves to be a pivotal year in the history of lithography.  Why should 2016 be any different?  Our industry moves too fast to allow a slack year.

I am frequently reminded of Sturtevant’s Law, not just because it is cute and funny (though it is), but because behind the humor lies a profound truth.  Sturtevant’s Law says that the end of optical lithography is 6 – 7 years away.  Always has been, always will be.  When I started in the field of lithography way back in 1983, Sturtevant’s Law was as yet unformulated but nonetheless in full swing.  X-ray or e-beam lithography was sure to take over by 1990 since it was obvious that optical lithography could not cross the 1 micron barrier.

This was but one of many, many failed predictions of the end of optical lithography.  But the fundamental truth behind Sturtevant’s Law is this:  we always know what we are doing for the next node (in 2 – 3 years), and are pretty sure about the node after that, but we have almost no visibility into what comes next.  We know all of the unsolved problems looming beyond the 6 year horizon, and can’t quite picture the solutions.  Sturtevant’s Law is a statement about our research and development timelines and how they relate to the pace of Moore’s Law.

But while Sturtevant’s Law has been in force for over 30 years, I’m afraid that it may be coming to an untimely end.  The reason is simple:  we no longer have good visibility out to two nodes (6 years).  We have a just barely reasonable impression about what the next node will bring, and are sure that the node after that is impossible.  The end of optical lithography is no longer 6 -7 years away, it is 2 – 3 years away, and even that time frame seems impossibly distant and opaque.

Our angst is about more than just lithography.  Of course, we lithographers know that the industry moves to the pace that we set.  Still, it is disconcerting to believe that a slowdown in lithography means the end of Moore’s Law.  Yet that is what is at stake.  In 2016, we must discover a path that keeps Moore’s Law moving forward, or watch Moore’s Law fall flat.

But a slowdown of Moore’s Law has already begun.  Intel’s 14-nm node was a year late, and Intel has admitted that its 10-nm node will also be late, on a 3-year node pace rather than the historic 2-year cycle.  TSMC has not admitted the slow-down, but is experiencing it anyway.  They created a “faux” node, a 16-nm product line that has the same dimensions and density as the previous 20-nm node.  Revealingly, when the 16-nm node came online last year, they did not report the revenues of that node separately as had been their normal practice, but rather began to lump the 16 and 20-nm node revenues together in one bucket.  “Follow the money” was good advice coming from Deep Throat, and is good advice in the semiconductor industry as well.

Moore’s Law is slowing down because lithography is not keeping up.  Multiple patterning is expensive and process control is a serious problem.  No other solutions are available.  Now, this where EUV is supposed to come in and save the day, right?

Alas, EUV is late.  ASML has made very good progress in the last two years, but that progress has been enough to keep EUV late, not enough to catch up with the industry need.  Anyone who has read these conference blogs before knows that I have been and continue to be an EUV skeptic.  But for the first time in over 20 years of development, I finally see a glimmer of hope for EUV.

Time is the enemy of all lithography development programs.  The demands of lithography move at an unrelenting pace, and even the slightest schedule slip in a lithography development program is the kiss of death.  EUV is late, an almost unmistakable sign of failure, and yet finally there is hope.  And here is the reason.

EUV was supposed to save Moore’s Law.  But instead, the slowdown of Moore’s Law may save EUV.

The 10-nm node will be two years late compared to the original schedule (naming games aside), as we are now on a three-year Moore’s Law cycle.  But since EUV is more than two years late, it still could not impact that node.  How late will the 7-nm node be?  Could it be late enough to use EUV?  That is a distinct possibility.

The big picture of lithography is bigger than the picture we will see at the SPIE Advanced Lithography Symposium in 2016, since the big picture involves the macroeconomics of the semiconductor industry itself.  But what we will see here this week is still big and very important.  How painful is multiple patterning really?  How close is directed self-assembly to being production worthy?  What is the status of nanoimprint manufacturing for Flash production?  Has there been any progress in taming the roughness beast?  And of course, what about EUV source power?

There are always many questions coming into the start of the SPIE lithography conference.  I am excited to start learning the answers.