SPIE Advanced Lithography and Patterning Symposium 2023 – day 1

The plenary session Monday morning began with awards.  I was glad to hear that 27 students received grants from SPIE to cover their registration and travel to the conference (Fractilia is one of the corporate sponsors of these student grants and I was happy to meet some of those students later that day at a student-mentor lunch).  Tony Yen of ASML was this year’s winner of the Frits Zernike Award for Microlithography – congratulations!  The Kingslake Award for Optical Design is not usually presented at this conference, but this year’s winner Wilhelm Ulrich chose to receive that honor here since his work at Zeiss in designing lithographic lenses was the reason for this prestigious reward.

Was saw eight new SPIE fellows from our community inducted this year, seven of whom were on hand to be recognized for this achievement: Martin Burkhardt of IBM, Debbie Gustafson of Energetiq, Larry Melvin of Synopsis, Warren Montgomery of EMD Electronics, Linyong Pang of D2S, Takashi Sato of KIOXIA, Geert Vandenberghe of imec, and Yayi Wei of the Chinese Institute of Microelectronics.  A great group of fellows, indeed.

As I glanced back across the room before the start of the first plenary talk, I was gratified to see what once was a familiar site:  the largest lecture hall at the San Jose convention center was full to overcrowding, standing room only, with an overflow room set up to accommodate the rest.  We are back!  And our first plenary speaker of the day, Martin van den Brink of ASML, did not disappoint in a talk densely packed with interesting information.  Martin gave a plenary speech 15 years earlier where he projected scaling for the coming 15 years, so it was fun to hear him compare those projections to reality (he did better than most prognosticators) and then try it again, providing ASML’s vision of Moore’s Law in the coming decade.  Of course, he predicted lithography scaling would continue – it is in ASML’s DNA (and I suspect in their corporate bylaws as well).

Martin described the well-known evolution of Moore’s Law away from transistor scaling towards system scaling, especially for energy efficient performance (EEP).  Still, he remains hopeful that DRAM scaling will continue down to 15 nm pitch, and vertical NAND flash will grow to 1000 transistors tall!  ASML is pushing massive e-beam inspection to approach optical defect inspection in terms of productivity, a tough road, but I am sure they will be at least partially successful.  I was almost numbed to see projections of DUV scanner throughput to 400 wafers per hour, and even 500 wph!  My first thought was “that’s impossible”, but I’ve come to understand that these kinds of things are impossible only until ASML does them.  Of course sustainability is on everyone’s mind nowadays, so Martin addressed the 100 kW-hour per finished wafer energy expenditure for lithography.  The goal is for that number to at least remain the same, if not go down over time.  As for EUV source power, 500W is said to be on the way, 600W is being demonstrated, and 800W is on the roadmap.  Each increase is EUV source power is of course very challenging.

Maybe the most interesting part of his talk (at least for me) was the new optical designs that removed one mirror from both the 0.33 and 0.55 NA systems (from the illuminator, it appeared).  Since each mirror has less than 70% reflectivity, the removal of one mirror represents a significant throughput advantage for these EUV scanners. He also described ASML’s plans for EUV “hyper” NA, a 0.75 NA design.  But without polarization (which Martin admitted would not happen), the image contrast benefit of the higher NA is reduced, so that a cost/benefit analysis of hyper-NA EUV seems clearly against it ever becoming a reality.  Time will tell, but of course ASML must have a roadmap.

I did not stick around for the second plenary talk on the Chips Act (I’m not going to apply for any of that money), so it was off to the regular conference papers.  Martin Weiss of Intel talked about modeling the matching of high-NA EUV two-field to low-NA one field difficulties.  It seems Intel is still hoping to jump back into the lead in scaling by being the first to implement high-NA EUV into production.  Good luck to them – that is going to be very hard, and probably late.  Zhigang Wang and B.H. Lee of Hitachi High Technology talked on the future of CD-SEM metrology, emphasizing the need for 0.01 nm tool-to-tool matching (or at least of that order) without giving much of a hint how they might achieve that.  I agree with them that SEM tool matching needs significantly more attention.  Ryosuke Kizu of the National Metrology Institute of Japan gave another good paper this year on their metrological tilt-AFM tool.  This year they looked at how SEM exposure of resist results in sidewall roughness smoothing – an important topic for those of us trying to measure resist feature roughness using top-down CD-SEMs.  I hope Kizu can partner with a CD-SEM owner to turn this interesting experimental technique into results useful to semiconductor metrologists.

In the EUV+Optical/Resist joint session in the afternoon there were a pair of papers by FujiFILM followed by Samsung looking at developer and rinse effects on line-edge roughness.  Both seemed to indicate that NTD (negative tone develop) using solvent developer for EUV held some promise for roughness and defect reduction, but I would consider these results preliminary at best.  I hope they work with imec to validate this behavior.

While there were a few other good papers late in the afternoon, my business obligations prevented me from attending them.  I had to go to the Fractilia Happy Hour at Uproar Brewing.  Ah, the burdens of entrepreneurship.

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