“We have experienced some delay in EUV, basically caused by delays in developing the light source”, said Peter Wennink, ASML’s financial chief.

With that understatement, ASML succinctly explained its rationale for offering $2.6B in cash (25%) and stock (75%) to buy San Diego-based Cymer, the leading developer of EUV sources. Over the last year, ASML has sent about 500 of their engineers to work at Cymer’s EUV source development labs. But as EUV source development falls further behind schedule, it has become obvious that this infusion of manpower was not enough.

There is a nice symmetry at work here. Earlier this year ASML got Intel, TSMC and Samsung to buy 23% of ASML and invest in ASML R&D to boot. Just as the chip makers invested in their key supplier ASML to provide maximum financial stability during a turbulent time, ASML is investing in one of its most critical suppliers to make sure they keep the faith during a very difficult time. Will this help speed up EUV source development? I doubt it. But it will probably help prevent a worsening of the schedule and keep Cymer’s focus where it needs to be.

While everyone concentrates on Cymer’s EUV source development, it is important to remember that ASML’s and Cymer’s cash cow is 193-nm immersion lithography. As ASML dumps cash into EUV development, it has remained profitable due to its growing market share of 193-nm tools (now about 80%). But Cymer only supplies about half of the 193-nm lasers that ASML needs. The other half comes from Gigaphoton (formed in 2000 as a joint venture of Komatsu and Ushio). What will happen to Gigaphoton in the long term? You can bet they are trying to figure that out themselves about now. And what does this deal say about ASML’s faith in Gigaphoton’s EUV source development efforts? It seems ASML is willing to put all of its source eggs in one basket.

Alas, I was not able to attend the Bacus maskmaking conference last week in Monterey, California. Although smaller now than in its heyday, it is still a fun conference to go to. But thanks to some talented and enterprising Baccanalians, a little of the flavor of the conference is available on YouTube:

http://www.youtube.com/watch?v=2HgJc9UMvd0&feature=share

I don’t know who all the folks are who made this, though I do recognize Mark Mason (the Aggie) and it must certainly be Tony Vacca on the drums.

For a little history on Bacus entertainment, look here.

After posting on Why 450-mm Wafers and Why the Big Players Like 450-mm Wafers, I received a few comments from friends in the equipment supplier community talking about the effect of wafer-size transitions on the suppliers of process and metrology tools for semiconductor manufacturing. So, based on their inputs and further reflection, here are a few more thoughts on 450-mm wafers.

It is expensive to develop equipment to process larger wafers. If an equipment supplier spends a boatload of money developing new equipment, they want to sell that new equipment for a lot of money in order to recoup their investment. But their customers, the chip makers, don’t want the equipment prices to rise too much, or else the cost advantage of the larger wafer size will disappear. The goal should be a win-win sharing of the benefits of a lager wafer: the chip makers get a lower manufacturing cost per chip and the equipment makers get a higher margin on their equipment, thus paying off their R&D and making more money after that.

There is a general feeling in the industry that the transition to 300-mm wafers didn’t work out equitably: the equipment suppliers made all the investments, and the chip makers got all the benefits. And while I’m sure this version of the story is somewhat slanted, still we have seen most equipment suppliers dragging their feet on 450-mm tool development. They want the chip companies to pay up-front for development. Chip companies in turn want to get governments to foot the bill (why should a highly profitable company like Intel pay the costs needed to ensure future profits if they can get the state of New York to pay instead?). And so it has begun: the Global 450 Consortium funding tool R&D, and Intel, TSMC, and Samsung paying litho supplier ASML billions of dollars directly for 450-mm tool development.

How will a transition to 450-mm wafers affect the equipment suppliers? One effect is similar to that experienced by the chip makers: the small guys won’t survive. Only the bigger players can afford the development costs for 450-mm wafer size tools. But there has traditionally been a second effect: even the big players can’t afford the development costs of new process equipment on multiple wafer sizes.

When the industry moved to 300-mm wafers, new process tools were developed for 300-mm wafers only. Chip companies that stuck to 200-mm wafers couldn’t get the latest and greatest tools for the smaller wafer size. They were stuck in the past. Not only did they have a cost disadvantage compared to 300-mm fabs, they had a technology disadvantage as well. Staying up to speed on Moore’s Law required moving to 300-mm wafers.

Will the same thing happen at 450 mm? Maybe, but I’m not convinced that it is inevitable. As I said before, the move to 450-mm wafers will not likely be the slam-dunk cost savings that many people hope. If the cost advantage is only 10%, I suspect many companies will choose to stick with 300-mm wafers. But will the next generation of process tools be available at the smaller wafer size? If new 300-mm wafer fabs are being built, you can bet that equipment suppliers will scramble to provide them with tools.

All in all, I think the move to 450-mm wafers will be a mess. The timing is problematic, the economics are problematic, and the resemblance of the future to the past is not likely to be strong. Somehow, though, we’ll figure something out. We always do.

The reason semiconductor manufacturers like the idea of 450-mm wafers is easy to understand: bigger wafers should lower the per-chip cost of manufacturing. But as I mentioned in my last post, this per-chip cost advantage doesn’t apply to lithography. Each time a wafer size is increased, only the non-litho (per-chip) costs go down, and so lithography costs take up a bigger portion of the overall costs. A corollary to this economic reality is that as lithography costs go up as a fraction of the total costs, the benefits of a larger wafer size go down. Past wafer size transitions have netted a 30% manufacturing cost reduction. The transition to 450-mm wafers will give at best a 20% cost reduction, and possibly only a 10% reduction.

Of course, these numbers are projections, and all projections are based on assumptions. It is possible to make more optimistic assumptions than I have, and that is probably what Intel, TSMC and the other big players are doing when they heavily promote 450-mm wafers. But why are the big guys so optimistic about 450-mm wafers? And why now?

As I briefly mentioned in my last post, for the switch to larger wafer sizes to be economically feasible two things must happen. First, the switch must enable a lower manufacturing cost per chip. The big players are hoping for a 30% cost reduction, but I am predicting a 10 – 20% benefit. Second, there must be sufficient demand for the chips being produced to justify a higher volume factory. A 450-mm fab will have at least double the output (in terms of chips) as a 300-mm fab. Thus, the demand for those chips must at least double to justify the building of a 450-mm fab. That’s a huge volume of chips, since 300-mm fabs are already exceedingly high-volume.

So an important effect of each wafer transition is that low-volume manufacturers can no longer compete. A 30% cost disadvantage is hard to overcome, and without the volume demand a new fab at the larger wafer size isn’t justified. The result? A successful wafer size transition is accompanied by a host of consolidations and chip companies going fabless (or fab-lite). This has happened again and again over the years. Only the biggest players survive, and the survivors get bigger.

Today, we have Intel, Samsung, Toshiba and TSMC at the top of the chip-making pyramid. But UMC, GlobalFoundries, Hynix, and Micron remain competitive irritants. What to do? A successful transition to 450-mm wafers will likely solve the problem for the big players. If 450-mm wafers result in a 20 – 30% cost advantage over 300-mm wafers, then any standard-process chip in a cost competitive space will have to be made in a 450-mm fab. But only a few of these $10B fabs will have to be built to supply that demand. And those fabs will be built by the biggest players, leaving the second tier manufacturers out of luck, and possibly out of business.

So why shouldn’t Intel, Samsung, and TSMC be bullish on 450-mm? If it works, it will mean that their dominance in the semiconductor world will be complete (maybe even pushing Toshiba out of the picture). And if EUV succeeds in keeping litho costs down, this scenario is all the more likely.

But personally I don’t think EUV will be successful at putting a lid on litho cost. As a result, I think the cost advantage of 450-mm will be closer to 10% than the 20 – 30% hoped for by the big guys. And while 10% may still be worth it for the highest-volume players, it won’t be enough to put the 300-mm fab world out of business.

That leaves one more ugly point to consider. If a transition to 450-mm wafers gives a per-chip cost reduction that is not sufficiently large to counter the rising costs of litho, then the per-chip costs overall might be higher (and maybe a lot higher) for new technology nodes. What will happen to Moore’s Law if moving to the next node no longer decreases the cost of a transistor?

We live in interesting times, and getting more interesting each day.

Why is 450-mm development so important to Intel (and Samsung and TSMC)?

A few years ago, Intel and TSMC began heavily promoting the need for a transition from the current standard silicon wafer size, 300 mm, to the new 450-mm wafers. While many have worked on 450-mm standards and technology for years, it is only recently that the larger wafer has received enough attention and support (not to mention government funding) to believe that it may actually become real. While there has been much talk about the need for a larger wafer, I’d like to put my spin on the whole debate.

First, a bit of history. Silicon wafer sizes have been growing gradually and steadily for the last 50 years, from half-inch and one-inch silicon to today’s 300-mm diameter wafers. The historical reasons for this wafer size growth were based on three related trends: growing chip size, growing demand for chips, and the greater chip throughput (and thus lower chip cost) that the larger wafer sizes enabled. And while chip sizes stopped increasing about 15 years ago, the other two factors have remained compelling. The last two wafer size transitions (6 inch to 8 inch/200 mm, and 200 mm to 300 mm) each resulted in about a 30% reduction in the cost per area of silicon (and thus cost per chip). And since our industry is enamored with the thought that the future will look like the past, we are hoping for a repeat performance with the transition to 450-mm wafers.

But a closer look at this history, and what we can expect from the future, reveals a more complicated picture.

First, how does increasing wafer size lower the cost per unit area of silicon? Consider one process step as an example – etch. Maximum throughput of an etch tool is governed by two basic factors: wafer load/unload time and etch time. With good engineering there is little reason why these two times won’t remain the same as the wafer size increases. Thus, wafer throughput remains constant as a function of wafer size, so that chip throughput improves as the wafer size increases. But “good engineering” is not free, and it takes work to keep the etch uniformity the same for a larger wafer. The larger etch tools also cost more money to make. But if the tool cost does not increase as fast as the wafer area, the result is a lower cost per chip. This is the goal, and the reason why we pursue larger wafer sizes.

As a simplified example, consider a wafer diameter increase of 1.5X (say, from 200 mm to 300 mm). The wafer area (and thus the approximate number of chips) increases by 2.25. If the cost of the etcher, the amount of fab floor space, and the per-wafer cost of process chemicals all increase by 30% at 300 mm, the cost per chip will change by 1.3/2.25 = 0.58. Thus, the etch cost per chip will be 42% lower for 300-mm wafers compared to 200-mm wafers.

While many process steps have the same fundamental scaling as etch – wafer throughput is almost independent of wafer size – some process steps do not. In particular, lithography does not scale this way. Lithography field size (the area of the wafer exposed at one time) has been the same for nearly 20 years (since the era of step-and-scan), and there is almost zero likelihood that it will increase in the near future. Further, the exposure time for a point on the wafer for most litho processes is limited by the speed with which the tool can step and scan the wafer (since the light source provides more than enough power).

Like etch, the total litho process time is the wafer load/unload time plus the exposure time. The load time can be kept constant as a function of wafer size, but the exposure time increases as the wafer size increases. In fact, it takes great effort to keep the scanning and stepping speed from slowing down for a larger wafer due to the greater wafer and wafer stage mass that must be moved. And since wafer load/unload time is a very small fraction of the total process time, the result for lithography is a near-constant wafer-area throughput (rather than the constant wafer throughput for etch) as wafer size is changed.

One important but frequently overlooked consequence of litho throughput scaling is that each change in wafer size results in an increase in the fraction of the wafer costs caused by lithography. In the days of 6-inch wafers, lithography represented roughly 20 – 25% of the cost of making a chip. The transition to 200-mm (8-inch) wafers lowered the (per-chip) cost of all process steps except lithography. As a result, the overall per-chip processing costs went down by about 25 – 30%, but the per-chip lithography costs remained constant and thus become 30 – 35% of the cost of making a chip.

The transition to 200-mm wafers increased the wafer area by 1.78. But since lithography accounted for only 25% of the chip cost at the smaller 6-inch wafer size, that area improvement affected 75% of the chip cost and gave a nice 25 – 30% drop in overall cost. The transition to 300-mm wafers gave a bigger 2.25X area advantage. However, that advantage could only be applied to the 65% of the costs that were non-litho. The result was again a 30% reduction in overall per-chip processing costs. But after the transition, with 300-mm wafers, lithography accounted for about 50% of the chip-making cost.

Every time wafer size increases, the importance of lithography to the overall cost of making a chip grows.

And there lies the big problem with the next wafer size transition. Each wafer size increase affects only the non-litho costs, but those non-litho costs are becoming a smaller fraction of the total because of wafer size increases. Even if we can achieve the same cost savings for the non-litho steps in the 300/450 transition as we did for the 200/300 transition, its overall impact will be less. Instead of the hoped-for 30% reduction in per-chip costs, we are likely to see only a 20% drop in costs, at best.

So we must set our sights lower: past wafer size transitions gave us a 30% cost advantage, but 450-mm wafers will only give us a 20% cost benefit over 300-mm wafers. Is that good enough? It might be, if all goes well. But the analysis above applies to a world that is quickly slipping away – the world of single-patterning lithography. If 450-mm wafer tools were here today, maybe this 20% cost savings could be had. But shrinking feature sizes are requiring the use of expensive double-patterning techniques, and as a result lithography costs are growing. They are growing on a per-chip basis, and as a fraction of the total costs. And as lithography costs go up, the benefits of a larger wafer size go down.

Consider a potential “worst-case” scenario: at the time of a transition to 450-mm wafers, lithography accounts for 75% of the cost of making a chip. Let’s also assume that switching to 450-mm wafers does not change the per-chip litho costs, but lowers the rest of the costs by 40%. The result? An overall 10% drop in the per-chip cost. Is the investment and effort involved in 450-mm development worth it for a 10% drop in manufacturing costs? And is that cost decrease enough to counter rising litho costs and keep Moore’s Law alive?

Maybe my worst-case scenario is too pessimistic. In five or six years, when a complete 450-mm tool set might be ready, what will lithography be like? In one scenario, we’ll be doing double patterning with EUV lithography. Does anyone really believe that this will cost the same as single-patterning 193-immersion? I don’t. And what if 193-immersion quadruple patterning is being used instead? Again, the only reasonable assumption will be that lithography accounts for much more than 50% of the cost of chip production.

So what can we conclude? A transition to 450-mm wafers, if all goes perfectly (and that’s a big if), will give us less than 20% cost improvement, and possibly as low as 10%. Still, the big guys (Intel, TSMC, IBM, etc.) keep saying that 450-mm wafers will deliver 30% cost improvements. Why? Next time, I’ll give my armchair-quarterback analysis as to what the big guys are up to.